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Searched refs:CTZ (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dknown-non-zero.ll17 ; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
43 ; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
44 ; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
144 ; CHECK-NEXT: ret i64 [[CTZ]]
167 ; CHECK-NEXT: ret i64 [[CTZ]]
190 ; CHECK-NEXT: ret i64 [[CTZ]]
213 ; CHECK-NEXT: ret i64 [[CTZ]]
236 ; CHECK-NEXT: ret i64 [[CTZ]]
259 ; CHECK-NEXT: ret i64 [[CTZ]]
282 ; CHECK-NEXT: ret i64 [[CTZ]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dcttz-ctlz.ll23 ; SLOW-NEXT: [[CTZ:%.*]] = phi i64 [ 64, [[ENTRY:%.*]] ], [ [[Z]], [[COND_FALSE]] ]
24 ; SLOW-NEXT: ret i64 [[CTZ]]
40 ; FAST_LZ-NEXT: [[CTZ:%.*]] = phi i64 [ 64, [[ENTRY:%.*]] ], [ [[Z]], [[COND_FALSE]] ]
41 ; FAST_LZ-NEXT: ret i64 [[CTZ]]
58 ; SLOW-NEXT: [[CTZ:%.*]] = phi i64 [ 64, [[ENTRY:%.*]] ], [ [[Z]], [[COND_FALSE]] ]
59 ; SLOW-NEXT: ret i64 [[CTZ]]
70 ; FAST_TZ-NEXT: [[CTZ:%.*]] = phi i64 [ 64, [[ENTRY:%.*]] ], [ [[Z]], [[COND_FALSE]] ]
71 ; FAST_TZ-NEXT: ret i64 [[CTZ]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/AArch64/
H A Dcttz-ctlz.ll6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/Mips/
H A Dcttz-ctlz.ll6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp532 unsigned CTZ = DemandedMask.countTrailingZeros(); in SimplifyDemandedUseBits() local
535 C->countTrailingZeros() == CTZ) { in SimplifyDemandedUseBits()
536 Constant *ShiftC = ConstantInt::get(VTy, CTZ); in SimplifyDemandedUseBits()
905 unsigned CTZ = DemandedMask.countTrailingZeros(); in SimplifyDemandedUseBits() local
907 CTZ >= C->getActiveBits()) in SimplifyDemandedUseBits()
917 unsigned CTZ = DemandedMask.countTrailingZeros(); in SimplifyDemandedUseBits() local
919 CTZ >= C->getBitWidth() - C->countLeadingOnes()) in SimplifyDemandedUseBits()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp245 case RISCV::CTZ: in isSignExtendingOpW()
H A DRISCVInstrInfoZb.td486 def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">,
1020 def : PatGpr<cttz, CTZ>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td86 defm CTZ : UnaryInt<cttz, "ctz ", 0x68, 0x7a>;
/llvm-project-15.0.7/clang/docs/
H A DReleaseNotes.rst692 - Intrinsics added for the RISC-V CLZ and CTZ instructions in the Zbb
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2562 unsigned CTZ = DemandedBits.countTrailingZeros(); in SimplifyDemandedBits() local
2564 if (C && C->getAPIntValue().countTrailingZeros() == CTZ) { in SimplifyDemandedBits()
2566 SDValue AmtC = TLO.DAG.getConstant(CTZ, dl, ShiftAmtTy); in SimplifyDemandedBits()