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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-ctlz.mir15 ; CHECK: $d0 = COPY [[CTLZ]](<8 x s8>)
35 ; CHECK: $d0 = COPY [[CTLZ]](<4 x s16>)
55 ; CHECK: $d0 = COPY [[CTLZ]](<2 x s32>)
75 ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY1]](s64)
76 ; CHECK: $d0 = COPY [[CTLZ]](s64)
97 ; CHECK: $s0 = COPY [[CTLZ]](s32)
118 ; CHECK: $q0 = COPY [[CTLZ]](<16 x s8>)
138 ; CHECK: $q0 = COPY [[CTLZ]](<8 x s16>)
158 ; CHECK: $q0 = COPY [[CTLZ]](<4 x s32>)
180 ; CHECK: $s0 = COPY [[CTLZ]](s32)
[all …]
H A Dlegalize-cttz-zero-undef.mir17 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
18 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
40 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
41 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
63 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
64 ; CHECK: $w0 = COPY [[CTLZ]](s32)
84 ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
85 ; CHECK: $x0 = COPY [[CTLZ]](s64)
H A Dlegalize-cttz.mir17 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
18 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
40 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
41 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
63 ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
64 ; CHECK: $w0 = COPY [[CTLZ]](s32)
84 ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
85 ; CHECK: $x0 = COPY [[CTLZ]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dctlz.mir14 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
15 ; MIPS32: $v0 = COPY [[CTLZ]](s32)
37 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
39 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
H A Dcttz.mir19 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
20 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
48 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
49 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ]]
90 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
91 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
130 ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
131 ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/AMDGPU/
H A Dcttz-ctlz.ll8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
128 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
129 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
147 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
148 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dctlz.mir15 ; MIPS32: [[CTLZ:%[0-9]+]]:gprb(s32) = G_CTLZ [[COPY]](s32)
16 ; MIPS32: $v0 = COPY [[CTLZ]](s32)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfls.ll33 ; CHECK-NEXT: [[CTLZ:%.*]] = call i64 @llvm.ctlz.i64(i64 %z, i1 false), !range !0
34 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[CTLZ]] to i32
H A Dintrinsics.ll305 ; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[OR]], i1 true), !range [[RNG2:![…
306 ; CHECK-NEXT: ret i32 [[CTLZ]]
316 ; CHECK-NEXT: [[CTLZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[OR]], i1 true)
317 ; CHECK-NEXT: ret <2 x i32> [[CTLZ]]
364 ; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[VALUE:%.*]], i1 false), !range [[RNG4…
365 ; CHECK-NEXT: ret i32 [[CTLZ]]
375 ; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false)
376 ; CHECK-NEXT: ret <2 x i32> [[CTLZ]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/ARM/
H A Dctlz.ll4 ; Recognize CTLZ builtin pattern.
6 ; so do not insert builtin if CPU do not support CTLZ
68 ; Recognize CTLZ builtin pattern.
118 ; Recognize CTLZ builtin pattern.
160 ; Recognize CTLZ builtin pattern.
203 ; Recognize CTLZ builtin pattern.
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/NVPTX/
H A Dnon-vectorizable-intrinsic.ll7 ; CTLZ cannot be vectorized currently because the second argument is a scalar
10 ; Test causes an assert if LLVM tries to vectorize CTLZ.
H A Dnon-vectorizable-intrinsic-inseltpoison.ll7 ; CTLZ cannot be vectorized currently because the second argument is a scalar
10 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2883 { ISD::CTLZ, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2884 { ISD::CTLZ, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2885 { ISD::CTLZ, MVT::v32i16, 8 }, in getTypeBasedIntrinsicInstrCost()
2886 { ISD::CTLZ, MVT::v64i8, 20 }, in getTypeBasedIntrinsicInstrCost()
2887 { ISD::CTLZ, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2888 { ISD::CTLZ, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2889 { ISD::CTLZ, MVT::v16i16, 4 }, in getTypeBasedIntrinsicInstrCost()
2890 { ISD::CTLZ, MVT::v32i8, 10 }, in getTypeBasedIntrinsicInstrCost()
2891 { ISD::CTLZ, MVT::v2i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2892 { ISD::CTLZ, MVT::v4i32, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/X86/
H A Dctlz.ll5 ; Recognize CTLZ builtin pattern.
125 ; Recognize CTLZ builtin pattern.
194 ; Recognize CTLZ builtin pattern.
256 ; Recognize CTLZ builtin pattern.
312 ; Recognize CTLZ builtin pattern.
361 ; Recognize CTLZ builtin pattern.
418 ; Recognize CTLZ builtin pattern.
468 ; Recognize CTLZ builtin pattern.
528 ; Recognize CTLZ builtin pattern.
676 ; Recognize CTLZ builtin pattern.
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp181 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
253 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
254 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp146 case ARC::CTLZ: in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h702 CTLZ, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-bit-counting-pred.ll40 ; CTLZ
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp618 if (unsigned CTLZ = DemandedMask.countLeadingZeros()) { in SimplifyDemandedUseBits() local
619 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedUseBits()
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Drange.ll939 ; CHECK-NEXT: [[CTLZ:%.*]] = call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG5:![0…
940 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i16 [[CTLZ]] to i8
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp173 setOperationAction(ISD::CTLZ, T, Legal); in initializeHVXLowering()
260 setOperationAction(ISD::CTLZ, T, Custom); in initializeHVXLowering()
1695 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)}); in LowerHvxCttz()
2411 case ISD::CTLZ: in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp106 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
107 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp344 case ISD::CTLZ: in LegalizeOp()
785 case ISD::CTLZ: in Expand()
H A DSelectionDAGDumper.cpp435 case ISD::CTLZ: return "ctlz"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp343 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
368 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
386 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
1176 case ISD::CTLZ: in LowerOperation()
2232 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
2373 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()

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