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Searched refs:BaseOp (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp150 const MachineOperand *BaseOp; in runOnMachineFunction() local
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
155 BaseOp->isReg()) { in runOnMachineFunction()
156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
H A DAArch64InstrInfo.h151 const MachineOperand *&BaseOp,
H A DAArch64InstrInfo.cpp2551 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2552 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2555 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
2579 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
2611 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
2615 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
2620 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp109 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
129 BaseOp = &MI.getOperand(1); in getBaseOffset()
141 BaseOp = &MI.getOperand(1); in getBaseOffset()
146 BaseOp = &MI.getOperand(2); in getBaseOffset()
160 BaseOp = &MI.getOperand(1); in getBaseOffset()
H A DARMLoadStoreOptimizer.cpp1624 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1659 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1770 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1795 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1796 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
2731 MI->getOperand(BaseOp).setReg(NewBaseReg); in AdjustBaseAndOffset()
2871 int BaseOp = getBaseOperandIndex(Use); in DistributeIncrements() local
2872 if (BaseOp == -1) in DistributeIncrements()
2875 if (!Use.getOperand(BaseOp).isReg() || in DistributeIncrements()
3000 int BaseOp = getBaseOperandIndex(MI); in DistributeIncrements() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
785 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
788 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
810 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
812 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
814 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
H A DLanaiInstrInfo.h77 const MachineOperand *&BaseOp,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp430 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); in processAddUses() local
432 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
496 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses() local
498 BaseOp.setReg(NewReg); in updateAddUses()
499 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
500 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
H A DHexagonInstrInfo.cpp1166 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1172 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1181 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1189 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1194 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1210 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1227 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1232 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
3039 if (!BaseOp || !BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3041 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp107 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
148 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td660 field string BaseOp;
669 let BaseOp = name;
675 let BaseOp = name;
691 field string BaseOp;
699 let BaseOp = name;
705 let BaseOp = name;
H A DSIInstrInfo.cpp314 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
319 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
355 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
377 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
378 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
420 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
422 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
434 if (BaseOp) in getMemOperandsWithOffsetWidth()
435 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
437 if (BaseOp) in getMemOperandsWithOffsetWidth()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1071 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1079 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1223 const MachineOperand *BaseOp; in describeLoadedValue() local
1224 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1248 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
H A DMachineSink.cpp1016 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1019 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1022 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1035 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
H A DModuloSchedule.cpp895 const MachineOperand *BaseOp; in computeDelta() local
898 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
905 if (!BaseOp->isReg()) in computeDelta()
908 Register BaseReg = BaseOp->getReg(); in computeDelta()
H A DMachinePipeliner.cpp2121 const MachineOperand *BaseOp; in computeDelta() local
2124 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2131 if (!BaseOp->isReg()) in computeDelta()
2134 Register BaseReg = BaseOp->getReg(); in computeDelta()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h122 const MachineOperand *&BaseOp,
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1387 unsigned BaseOp = 0; in LowerXALUO() local
1394 BaseOp = M68kISD::ADD; in LowerXALUO()
1398 BaseOp = M68kISD::ADD; in LowerXALUO()
1402 BaseOp = M68kISD::SUB; in LowerXALUO()
1406 BaseOp = M68kISD::SUB; in LowerXALUO()
1413 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in LowerXALUO()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h633 const MachineOperand *&BaseOp,
H A DPPCInstrInfo.cpp2768 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2770 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
2772 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td1737 // let RowFields = BaseOp
1738 // All add instruction predicated/non-predicated will have to set their BaseOp
1741 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1742 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1743 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1337 const MachineOperand *&BaseOp, int64_t &Offset,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3955 unsigned BaseOp = 0; in lowerXALUO() local
3962 BaseOp = SystemZISD::SADDO; in lowerXALUO()
3967 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
3972 BaseOp = SystemZISD::UADDO; in lowerXALUO()
3977 BaseOp = SystemZISD::USUBO; in lowerXALUO()
3984 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
4020 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
4030 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
4038 BaseOp = SystemZISD::SUBCARRY; in lowerADDSUBCARRY()
4050 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry); in lowerADDSUBCARRY()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6923 unsigned BaseOp; in lowerAddSubSatToMinMax() local
6930 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
6935 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
6940 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
6945 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
6979 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); in lowerAddSubSatToMinMax()
6985 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); in lowerAddSubSatToMinMax()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp3707 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
3708 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
3717 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
3804 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
3806 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
3824 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3833 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()

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