1165       const MachineOperand &BaseOp = MI.getOperand(1);  in expandPostRAPseudo()  local
1166       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1172           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1180       const MachineOperand &BaseOp = MI.getOperand(1);  in expandPostRAPseudo()  local
1181       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1189           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)  in expandPostRAPseudo()
1194           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1203       const MachineOperand &BaseOp = MI.getOperand(0);  in expandPostRAPseudo()  local
1204       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1210           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
1219       const MachineOperand &BaseOp = MI.getOperand(0);  in expandPostRAPseudo()  local
1220       assert(BaseOp.getSubReg() == 0);  in expandPostRAPseudo()
1227           .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)  in expandPostRAPseudo()
1232           .addReg(BaseOp.getReg(), getRegState(BaseOp))  in expandPostRAPseudo()
3038   const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);  in getMemOperandsWithOffsetWidth()  local
3039   if (!BaseOp || !BaseOp->isReg())  in getMemOperandsWithOffsetWidth()
3041   BaseOps.push_back(BaseOp);  in getMemOperandsWithOffsetWidth()
3277   const MachineOperand &BaseOp = MI.getOperand(BasePos);  in getBaseAndOffset()  local
3278   if (BaseOp.getSubReg() != 0)  in getBaseAndOffset()
3280   return &const_cast<MachineOperand&>(BaseOp);  in getBaseAndOffset()