| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | 2010-03-05-ConstantFoldCFG.ll | 3 ; When BRCOND is constant-folded to BR, make sure that PHI nodes don't get
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 61 BRCOND, enumerator
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| H A D | AVRISelLowering.cpp | 102 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AVRTargetLowering()
257 NODE(BRCOND); in getTargetNodeName()
786 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, in LowerBR_CC()
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| H A D | AVRInstrInfo.td | 51 : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.h | 69 BRCOND, enumerator
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| H A D | M68kISelLowering.cpp | 124 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in M68kTargetLowering()
1339 case ISD::BRCOND: in LowerOperation()
1630 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
2378 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, in LowerBRCOND()
2408 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, in LowerBRCOND()
2452 return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC, in LowerBRCOND()
3418 return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0), in combineM68kBrCond()
3459 case M68kISD::BRCOND: in PerformDAGCombine()
3505 case M68kISD::BRCOND: in getTargetNodeName()
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| H A D | M68kInstrInfo.td | 143 def MxBrCond : SDNode<"M68kISD::BRCOND", MxSDT_BrCond, [SDNPHasChain]>;
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1001 BRCOND, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 73 BRCOND, // Conditional branch. enumerator
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| H A D | ARMISelLowering.cpp | 825 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC}); in ARMTargetLowering()
1426 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in ARMTargetLowering()
1679 MAKE_CASE(ARMISD::BRCOND) in getTargetNodeName()
5634 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in OptimizeVFPBrcond()
5746 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in LowerBR_CC()
5765 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
5769 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
10348 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
17931 if (N->getOpcode() == ISD::BRCOND) { in PerformHWLoopCombine()
18598 case ISD::BRCOND: in PerformDAGCombine()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 383 case ISD::BRCOND: return "brcond"; in getOperationName()
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| H A D | SelectionDAGBuilder.cpp | 2535 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSwitchCase()
2598 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitJumpTableHeader()
2723 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSPDescriptorParent()
2816 Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp, in visitBitTestHeader()
2875 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, in visitBitTestCase()
10802 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, in lowerWorkItem()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 73 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in BPFTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 147 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in ARCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 69 BRCOND, // Conditional branch instruction; "b.cond". enumerator
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| H A D | AArch64ISelLowering.cpp | 394 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in AArch64TargetLowering()
2052 MAKE_CASE(AArch64ISD::BRCOND) in getTargetNodeName()
5346 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
5372 case ISD::BRCOND: in LowerOperation()
7628 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
7695 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
7709 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); in LowerBR_CC()
7712 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, in LowerBR_CC()
19573 case AArch64ISD::BRCOND: in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 123 BRCOND, enumerator
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| H A D | X86ISelLowering.cpp | 345 setOperationAction(ISD::BRCOND , MVT::Other, Custom); in X86TargetLowering()
25814 return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
25847 Chain = DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, in LowerBRCOND()
25881 return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
25901 return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
32289 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
33476 NODE_NAME_CASE(BRCOND) in getTargetNodeName()
47251 case ISD::BRCOND: in combineCompareEqual()
52795 case X86ISD::BRCOND: in needCarryOrOverflowFlag()
52828 case X86ISD::BRCOND: in onlyZeroFlagUsed()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 99 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
418 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
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| H A D | SIISelLowering.cpp | 223 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in SITargetLowering()
4648 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
5163 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, in LowerBRCOND() argument
5165 SDLoc DL(BRCOND); in LowerBRCOND()
5167 SDNode *Intr = BRCOND.getOperand(1).getNode(); in LowerBRCOND()
5168 SDValue Target = BRCOND.getOperand(2); in LowerBRCOND()
5179 BR = findUser(BRCOND, ISD::BR); in LowerBRCOND()
5187 return BRCOND; in LowerBRCOND()
5201 Ops.push_back(BRCOND.getOperand(0)); in LowerBRCOND()
5214 BRCOND.getOperand(0) in LowerBRCOND()
[all …]
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| H A D | AMDGPUISelDAGToDAG.cpp | 677 case ISD::BRCOND: in Select()
2225 assert(N->getOpcode() == ISD::BRCOND); in isCBranchSCC()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 87 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in LanaiTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 91 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in MSP430TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 344 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in MipsTargetLowering()
1218 case ISD::BRCOND: return lowerBRCOND(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 154 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in initSPUActions()
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