| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | TruncAssertSext.ll | 4 ; the source of the zext is an AssertSext node
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 61 AssertSext, enumerator
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| /llvm-project-15.0.7/llvm/test/DebugInfo/X86/ |
| H A D | dbg-value-transfer-order.ll | 21 ; interesting in this example is that the !range metadata produces an AssertSext
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 106 case ISD::AssertSext: return "AssertSext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 59 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
291 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
706 : ISD::AssertSext, in PromoteIntRes_FP_TO_XINT()
2411 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult()
3203 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
3207 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
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| H A D | LegalizeVectorOps.cpp | 680 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT()
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| H A D | SelectionDAGISel.cpp | 2825 case ISD::AssertSext: in SelectCodeCommon()
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| H A D | SelectionDAGBuilder.cpp | 891 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5480 case ISD::AssertSext: in getUnderlyingArgRegs()
9991 AssertOp = ISD::AssertSext; in LowerCallTo()
10544 AssertOp = ISD::AssertSext; in LowerArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 341 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 151 Op1->getOpcode() == ISD::AssertSext) in lowerUINT_TO_FP()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 499 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
658 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1424 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 467 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
815 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 467 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1532 case ISD::AssertSext: in keepsLowBits()
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| H A D | HexagonISelLowering.cpp | 1059 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1264 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1419 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
1427 N->getOpcode() != ISD::AssertSext &&
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 477 ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN}); in AMDGPUTargetLowering()
4140 case ISD::AssertSext: in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 1697 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2541 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val, in LowerFormalArguments()
2732 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3552 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
3603 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 913 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 729 def assertsext : SDNode<"ISD::AssertSext", SDT_assert>;
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4260 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
5183 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
6846 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, in truncateScalarIntegerArg()
17016 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext) in combineSHL()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 876 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && in SelectArithExtendedRegister()
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