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Searched refs:AndMask (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp97 const APInt &AndMask = N->getConstantOperandAPInt(1); in selectShiftMask() local
102 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
104 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
112 if (ShMask.isSubsetOf(AndMask | Known.Zero)) { in selectShiftMask()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1373 static void printSwizzleBitmask(const uint16_t AndMask, in printSwizzleBitmask() argument
1379 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1380 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1430 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; in printSwizzle() local
1434 if (AndMask == BITMASK_MAX && in printSwizzle()
1443 } else if (AndMask == BITMASK_MAX && in printSwizzle()
1454 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; in printSwizzle()
1470 printSwizzleBitmask(AndMask, OrMask, XorMask, O); in printSwizzle()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp133 APInt AndMask; in foldSelectICmpAnd() local
145 AndMask = *AndRHS; in foldSelectICmpAnd()
147 Pred, V, AndMask)) { in foldSelectICmpAnd()
149 if (!AndMask.isPowerOf2()) in foldSelectICmpAnd()
167 if (TC.getBitWidth() != AndMask.getBitWidth() || (TC ^ FC) != AndMask) in foldSelectICmpAnd()
174 V = Builder.CreateAnd(V, ConstantInt::get(SelType, AndMask)); in foldSelectICmpAnd()
202 unsigned AndZeros = AndMask.logBase2(); in foldSelectICmpAnd()
206 V = Builder.CreateAnd(V, ConstantInt::get(V->getType(), AndMask)); in foldSelectICmpAnd()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp737 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion() local
738 if (InsertMask & AndMask) in detectOrAndInsertion()
744 if (Used != (AndMask | InsertMask)) { in detectOrAndInsertion()
746 if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) in detectOrAndInsertion()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1952 const APInt &AndMask = N->getConstantOperandAPInt(1); in selectShiftMask() local
1957 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
1959 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
1967 if (ShMask.isSubsetOf(AndMask | Known.Zero)) { in selectShiftMask()
/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DDataFlowSanitizer.cpp273 uint64_t AndMask; member
1712 uint64_t AndMask = MapParams->AndMask; in getShadowOffset() local
1713 if (AndMask) in getShadowOffset()
1715 IRB.CreateAnd(OffsetLong, ConstantInt::get(IntptrTy, ~AndMask)); in getShadowOffset()
H A DMemorySanitizer.cpp352 uint64_t AndMask; member
900 CustomMapParams.AndMask = ClAndMask; in initializeModule()
1452 uint64_t AndMask = MS.MapParams->AndMask; in getShadowPtrOffset() local
1453 if (AndMask) in getShadowPtrOffset()
1455 IRB.CreateAnd(OffsetLong, ConstantInt::get(MS.IntptrTy, ~AndMask)); in getShadowPtrOffset()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DLocal.cpp3009 const APInt &AndMask = *C; in collectBitParts() local
3013 unsigned NumMaskedBits = AndMask.countPopulation(); in collectBitParts()
3025 if (AndMask[BitIdx] == 0) in collectBitParts()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp665 uint64_t AndMask = CSD->getZExtValue(); in getExtendTypeForNode() local
667 switch (AndMask) { in getExtendTypeForNode()
2021 uint64_t AndMask = 0; in isSeveralBitsExtractOpFromShr() local
2022 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask)) in isSeveralBitsExtractOpFromShr()
2032 unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm)); in isSeveralBitsExtractOpFromShr()
2033 if (BitWide && isMask_64(AndMask >> SrlImm)) { in isSeveralBitsExtractOpFromShr()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp7205 encodeBitmaskPerm(const unsigned AndMask, in encodeBitmaskPerm() argument
7211 (AndMask << BITMASK_AND_SHIFT) | in encodeBitmaskPerm()
7357 unsigned AndMask = 0; in parseSwizzleBitmaskPerm() local
7373 AndMask |= Mask; in parseSwizzleBitmaskPerm()
7376 AndMask |= Mask; in parseSwizzleBitmaskPerm()
7382 Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask); in parseSwizzleBitmaskPerm()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp5605 const APInt &AndMask = CAnd->getAPIntValue(); in visitANDLike() local
5612 unsigned MaskBits = AndMask.countTrailingOnes(); in visitANDLike()
5615 if (AndMask.isMask() && in visitANDLike()
5637 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
22744 SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT)); in visitVECTOR_SHUFFLE() local
22747 AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; in visitVECTOR_SHUFFLE()
22759 DAG.getBuildVector(IntVT, DL, AndMask))); in visitVECTOR_SHUFFLE()
24147 const APInt &AndMask = ConstAndRHS->getAPIntValue(); in SimplifySelectCC() local
24148 unsigned ShCt = AndMask.getBitWidth() - 1; in SimplifySelectCC()
24151 DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS), in SimplifySelectCC()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6604 uint64_t AndMask = *MaybeAndMask; in getExtendTypeForInst() local
6605 switch (AndMask) { in getExtendTypeForInst()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17432 uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); in PerformShiftCombine() local
17434 if (AndMask == 255 || AndMask == 65535) in PerformShiftCombine()
17436 if (isMask_32(AndMask)) { in PerformShiftCombine()
17437 uint32_t MaskedBits = countLeadingZeros(AndMask); in PerformShiftCombine()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp3022 APInt AndMask = APInt::getSignedMaxValue(bitsize); in EmitBuiltinExpr() local
3024 Builder.CreateAnd(IntV, llvm::ConstantInt::get(IntTy, AndMask)); in EmitBuiltinExpr()