| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1628 Instruction *And1 = dyn_cast<Instruction>(I->getOperand(1)); in setupPreSimplifier() local
1629 if (!And0 || !And1) in setupPreSimplifier()
1632 And1->getOpcode() != Instruction::And) in setupPreSimplifier()
1634 if (And0->getOperand(1) != And1->getOperand(1)) in setupPreSimplifier()
1637 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), in setupPreSimplifier()
1760 Instruction *And1 = dyn_cast<Instruction>(Xor->getOperand(1)); in setupPostSimplifier() local
1763 std::swap(And0, And1); in setupPostSimplifier()
1772 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1), C0); in setupPostSimplifier()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 857 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine() local
870 if (And1.getOpcode() == ISD::AND && in performORCombine()
871 And1.getOperand(0).getOpcode() == ISD::SHL) { in performORCombine()
873 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || in performORCombine()
881 SDValue Shl = And1.getOperand(0); in performORCombine()
908 bool isConstCase = And1.getOpcode() != ISD::AND; in performORCombine()
909 if (And1.getOpcode() == ISD::AND) { in performORCombine()
910 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) in performORCombine()
927 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 546 Instruction *And1 = BinaryOperator::CreateAnd(I->getOperand(0), One); in SimplifyDemandedUseBits() local
547 return InsertNewInstWith(And1, *I); in SimplifyDemandedUseBits()
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| H A D | InstCombineCasts.cpp | 1073 Value *And1 = Builder.CreateAnd(Lshr, ConstantInt::get(X->getType(), 1)); in transformZExtICmp() local
1074 return replaceInstUsesWith(Zext, And1); in transformZExtICmp()
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| H A D | InstCombineCompares.cpp | 4443 Value *And1 = Builder.CreateAnd(BO0->getOperand(0), Mask); in foldICmpBinOp() local
4445 return new ICmpInst(Pred, And1, And2); in foldICmpBinOp()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2768 SDValue And1 = N->getOperand(1); in tryBitfieldInsertOpFromOr() local
2769 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
2771 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) && in tryBitfieldInsertOpFromOr()
2779 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
2783 SDValue Src = And1->getOperand(0); in tryBitfieldInsertOpFromOr()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6354 Register And1; in lowerFCopySign() local
6356 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); in lowerFCopySign()
6361 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); in lowerFCopySign()
6366 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); in lowerFCopySign()
6373 MIRBuilder.buildOr(Dst, And0, And1, Flags); in lowerFCopySign()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2576 SDValue And1 = TLO.DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), One); in SimplifyDemandedBits() local
2577 return TLO.CombineTo(Op, And1); in SimplifyDemandedBits()
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| H A D | DAGCombiner.cpp | 5999 SDValue And0 = And->getOperand(0), And1 = And->getOperand(1); in combineShiftAnd1ToBitTest() local
6002 if (!isOneConstant(And1) || !And0.hasOneUse()) in combineShiftAnd1ToBitTest()
|