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Searched refs:xcc_id (Results 1 – 25 of 32) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c977 ring->xcc_id = xcc_id; in gfx_v9_4_3_compute_ring_init()
1102 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_sw_init()
1393 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
4391 xcc_id); in gfx_v9_4_3_inst_query_ras_err_count()
4447 xcc_id); in gfx_v9_4_3_inst_reset_ras_err_count()
4479 xcc_id); in gfx_v9_4_3_inst_enable_watchdog_timer()
4528 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_ip_print()
4551 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_ip_print()
4588 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_ip_dump()
4604 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { in gfx_v9_4_3_ip_dump()
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H A Damdgpu_gfx.h148 uint32_t xcc_id, uint32_t vmid);
294 u32 sh_num, u32 instance, int xcc_id);
304 u32 queue, u32 vmid, u32 xcc_id);
503 …elect_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (… argument
504 …_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe)… argument
528 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
530 unsigned hpd_size, int xcc_id);
533 unsigned mqd_size, int xcc_id);
536 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
538 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
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H A Damdgpu_gfx.c74 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
266 struct amdgpu_ring *ring, int xcc_id) in amdgpu_gfx_kiq_acquire() argument
312 ring->xcc_id = xcc_id; in amdgpu_gfx_kiq_init_ring()
313 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); in amdgpu_gfx_kiq_init_ring()
349 unsigned int hpd_size, int xcc_id) in amdgpu_gfx_kiq_init() argument
376 unsigned int mqd_size, int xcc_id) in amdgpu_gfx_mqd_sw_init() argument
582 j = i + xcc_id * adev->gfx.num_gfx_rings; in amdgpu_gfx_disable_kgq()
730 j = i + xcc_id * adev->gfx.num_gfx_rings; in amdgpu_gfx_enable_kgq()
1038 int xcc_id)) in amdgpu_gfx_ras_error_func() argument
1496 int i, r, xcc_id; in amdgpu_gfx_run_cleaner_shader() local
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H A Damdgpu_rlc.h236 void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
237 void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
339 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
340 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
H A Damdgpu_umr.h46 u32 xcc_id; member
50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Damdgpu_rlc.c38 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_enter_safe_mode() argument
40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_exit_safe_mode() argument
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
H A Dgfx_v9_0.h30 u32 instance, int xcc_id);
H A Damdgpu_virt.h407 u32 acc_flags, u32 hwip, u32 xcc_id);
409 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
418 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
H A Damdgpu_debugfs.c267 rd->id.grbm.instance, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
273 rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
286 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
299 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
304 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, rd->id.xcc_id); in amdgpu_debugfs_regs2_op()
358 rd->id.xcc_id = 0; in amdgpu_debugfs_regs2_ioctl()
429 amdgpu_gfx_select_se_sh(adev, rd->id.se, rd->id.sh, rd->id.cu, rd->id.xcc_id); in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
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H A Daqua_vanjaram.c174 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring); in aqua_vanjaram_update_partition_sched_list()
713 int xcc_id, uint8_t *mem_id) in __aqua_vanjaram_get_xcp_mem_id() argument
716 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; in __aqua_vanjaram_get_xcp_mem_id()
728 int r, i, xcc_id; in aqua_vanjaram_get_xcp_mem_id() local
748 xcc_id = ffs(xcc_mask) - 1; in aqua_vanjaram_get_xcp_mem_id()
750 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); in aqua_vanjaram_get_xcp_mem_id()
752 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in aqua_vanjaram_get_xcp_mem_id()
H A Damdgpu_virt.c1048 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) in amdgpu_virt_rlcg_reg_rw() argument
1067 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
1075 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1147 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1156 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); in amdgpu_sriov_wreg()
1167 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1176 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); in amdgpu_sriov_rreg()
H A Dsoc15.h110 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
H A Dgmc_v9_0.c564 int ret, xcc_id = 0; in gmc_v9_0_process_interrupt() local
581 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, in gmc_v9_0_process_interrupt()
583 if (xcc_id < 0) in gmc_v9_0_process_interrupt()
584 xcc_id = 0; in gmc_v9_0_process_interrupt()
586 vmhub = xcc_id; in gmc_v9_0_process_interrupt()
1943 int num_xcc, xcc_id; in gmc_v9_0_init_acpi_mem_ranges() local
1949 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
1950 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); in gmc_v9_0_init_acpi_mem_ranges()
H A Damdgpu.h1269 uint32_t xcc_id);
1278 uint32_t xcc_id);
1280 uint32_t reg, uint32_t v, uint32_t xcc_id);
1582 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1597 int xcc_id, in amdgpu_acpi_get_mem_info() argument
H A Dgfx_v12_0.c246 u32 sh_num, u32 instance, int xcc_id);
256 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
819 uint32_t xcc_id, in gfx_v12_0_read_wave_data() argument
856 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
868 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
879 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v12_0_select_me_pipe_q() argument
1347 int xcc_id = 0; in gfx_v12_0_sw_init() local
1492 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v12_0_sw_init()
1587 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
3749 int xcc_id) in gfx_v12_0_set_safe_mode() argument
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H A Damdgpu_mes.h259 uint32_t xcc_id; member
H A Dgfx_v9_0.c897 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
898 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1019 uint32_t xcc_id, uint32_t vmid) in gfx_v9_0_kiq_reset_hw_queue() argument
1025 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1047 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); in gfx_v9_0_kiq_reset_hw_queue()
1995 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v9_0_select_me_pipe_q() argument
2215 int xcc_id = 0; in gfx_v9_0_sw_init() local
2400 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v9_0_sw_init()
2478 u32 instance, int xcc_id) in gfx_v9_0_select_se_sh() argument
4873 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v9_0_set_safe_mode() argument
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H A Damdgpu_acpi.c1174 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, in amdgpu_acpi_get_mem_info() argument
1191 if (xcc_info->phy_id == xcc_id) { in amdgpu_acpi_get_mem_info()
H A Dgfx_v11_0.c298 u32 sh_num, u32 instance, int xcc_id);
309 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
310 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
1026 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1037 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
1048 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) in gfx_v11_0_select_me_pipe_q() argument
1572 int xcc_id = 0; in gfx_v11_0_sw_init() local
1764 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); in gfx_v11_0_sw_init()
1866 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
5109 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) in gfx_v11_0_set_safe_mode() argument
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/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c577 int xcc_id, err, inst = 0; in hiq_load_mqd_kiq_v9_4_3() local
581 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
601 int xcc_id, err, inst = 0; in destroy_hiq_mqd_v9_4_3() local
606 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
627 int inst = 0, xcc_id; in check_preemption_failed_v9_4_3() local
631 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
777 int xcc_id, err, inst = 0; in destroy_mqd_v9_4_3() local
785 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v9_4_3()
789 queue_id, xcc_id); in destroy_mqd_v9_4_3()
807 int xcc_id, err, inst = 0; in load_mqd_v9_4_3() local
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H A Dkfd_device_queue_manager.c149 int xcc_id; in program_sh_mem_settings() local
521 int xcc_id; in program_trap_handler_settings() local
795 int xcc_id; in dbgdev_wave_reset_wavefronts() local
1469 int xcc_id, ret; in set_pasid_vmid_mapping() local
1484 unsigned int i, xcc_id; in init_interrupts() local
2150 int xcc_id; in detect_queue_hang() local
2170 hang_info.xcc_id = xcc_id; in detect_queue_hang()
3693 int r = 0, xcc_id; in dqm_debugfs_hqds() local
3705 &n_regs, xcc_id); in dqm_debugfs_hqds()
3710 xcc_id, in dqm_debugfs_hqds()
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H A Dkfd_device_queue_manager.h225 int xcc_id; member
H A Dkfd_debug.c466 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id); in kfd_dbg_trap_set_dev_address_watch() local
481 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
489 xcc_id); in kfd_dbg_trap_set_dev_address_watch()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_12_ppt.c287 int xcc_id; in smu_v13_0_12_get_smu_metrics_data() local
293 xcc_id = GET_INST(GC, 0); in smu_v13_0_12_get_smu_metrics_data()
294 *value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); in smu_v13_0_12_get_smu_metrics_data()
350 int ret = 0, xcc_id, inst, i, j, k, idx; in smu_v13_0_12_get_gpu_metrics() local
385 xcc_id = GET_INST(GC, i); in smu_v13_0_12_get_gpu_metrics()
386 if (xcc_id >= 0) in smu_v13_0_12_get_gpu_metrics()
388 SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); in smu_v13_0_12_get_gpu_metrics()
H A Dsmu_v13_0_6_ppt.c1139 int xcc_id; in smu_v13_0_6_get_smu_metrics_data() local
1153 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
1154 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_smu_metrics_data()
2492 int ret = 0, xcc_id, inst, i, j, k, idx; in smu_v13_0_6_get_gpu_metrics() local
2541 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2542 if (xcc_id >= 0) in smu_v13_0_6_get_gpu_metrics()
2544 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]); in smu_v13_0_6_get_gpu_metrics()

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