Lines Matching refs:xcc_id

148 				   uint32_t xcc_id, uint32_t vmid);
294 			     u32 sh_num, u32 instance, int xcc_id);
295 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
297 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
300 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
304 				 u32 queue, u32 vmid, u32 xcc_id);
503 …elect_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (…  argument
504 …_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe)…  argument
524 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
528 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
530 			unsigned hpd_size, int xcc_id);
533 			   unsigned mqd_size, int xcc_id);
534 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
535 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
536 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
537 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
538 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
547 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
571 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);
572 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
580 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
586 				int xcc_id));