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Searched refs:TII (Results 1 – 25 of 513) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp105 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in INITIALIZE_PASS()
108 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i32, in INITIALIZE_PASS()
111 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV16rj), MVT::i32, in INITIALIZE_PASS()
125 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i16, in INITIALIZE_PASS()
128 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dp), MVT::i32, in INITIALIZE_PASS()
204 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in INITIALIZE_PASS()
206 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in INITIALIZE_PASS()
208 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true); in INITIALIZE_PASS()
211 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in INITIALIZE_PASS()
213 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true); in INITIALIZE_PASS()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
120 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
124 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
160 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
164 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
168 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp70 const PPCInstrInfo &TII; member in __anone5266a140111::PPCInstructionSelector
307 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
313 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
333 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
351 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
382 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
410 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
425 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
457 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
487 .constrainAllUses(TII, TRI, RBI); in selectI64ImmDirect()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp31 const R600InstrInfo *TII = nullptr; member in __anonb880ddb50111::R600ExpandSpecialInstrsPass
65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
68 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
74 TII = ST.getInstrInfo(); in runOnMachineFunction()
85 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
113 TII->addFlag(*PredSet, 0, MO_FLAG_MASK); in runOnMachineFunction()
139 TII->addFlag(*BMI, 0, MO_FLAG_MASK); in runOnMachineFunction()
142 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST); in runOnMachineFunction()
164 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
165 bool IsCube = TII->isCubeOp(MI.getOpcode()); in runOnMachineFunction()
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H A DSIPeepholeSDWA.cpp50 const SIInstrInfo *TII; member in __anon0f4c5ec60111::SIPeepholeSDWA
408 SrcMods->setImm(getSrcMods(TII, Src)); in convertToSDWA()
507 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
712 if (!TII->isSDWA(*Op1Inst)) in matchSDWAOperand()
762 if (!TII->isSDWA(*OtherInst)) in matchSDWAOperand()
867 if (!TII->canShrink(MI, *MRI)) in pseudoOpConvertToVOP2()
918 if (TII->isSDWA(Opc)) in isConvertibleToSDWA()
931 if (TII->isVOPC(Opc)) { in isConvertibleToSDWA()
956 if (TII->pseudoToMCOpcode(Opc) == -1) in isConvertibleToSDWA()
984 if (TII->isSDWA(Opcode)) { in convertToSDWA()
[all …]
H A DGCNDPPCombine.cpp56 const SIInstrInfo *TII; member in __anon94aa25420111::GCNDPPCombine
119 if (!TII->isVOP3(Op)) { in isShrinkable()
122 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
230 !(TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && in createDPPInst()
265 } else if (TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && in createDPPInst()
377 if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI)) in createDPPInst()
668 ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) || in combineDPPMov()
669 TII->isVOP3(OrigOp)) && in combineDPPMov()
671 TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) { in combineDPPMov()
712 if (TII->commuteInstruction(*NewMI)) { in combineDPPMov()
[all …]
H A DAMDGPUIGroupLP.cpp91 const SIInstrInfo *TII; member in __anon114cba190111::InstructionRule
106 : TII(TII), SGID(SGID) { in InstructionRule()
143 const SIInstrInfo *TII; member in __anon114cba190111::SchedGroup
237 : SGMask(SGMask), MaxSize(MaxSize), TII(TII), DAG(DAG) { in SchedGroup()
243 : SGMask(SGMask), MaxSize(MaxSize), SyncID(SyncID), TII(TII), DAG(DAG) { in SchedGroup()
863 : DAG(DAG), TII(TII) {} in IGLPStrategy()
1439 (TII->isVALU(MI) || TII->isMFMAorWMMA(MI) || TII->isSALU(MI) || in canAddMI()
1444 TII->isVALU(MI) && !TII->isMFMAorWMMA(MI) && !TII->isTRANS(MI)) in canAddMI()
1456 (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI)))) in canAddMI()
1461 (TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI)))) in canAddMI()
[all …]
H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anonbf22bd830111::R600PacketizerList
79 if (TII->isPredicated(*BI)) in getPreviousVector()
145 TII(ST.getInstrInfo()), in R600PacketizerList()
146 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
164 if (TII->isVector(MI)) in isSoloInstruction()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
203 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
205 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
225 isTransSlot = TII->isTransOnly(MI); in isBundlableWithCurrentPMI()
[all …]
H A DSIModeRegister.cpp166 if (TII->usesFPDPRounding(MI) || in getInstructionMode()
178 if (TII->getSubtarget().hasTrue16BitInsts()) { in getInstructionMode()
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
195 if (TII->getSubtarget().hasTrue16BitInsts()) { in getInstructionMode()
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
270 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
326 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
440 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
447 processBlockPhase1(BB, TII); in runOnMachineFunction()
455 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
[all …]
H A DR600EmitClauseMarkers.cpp34 const R600InstrInfo *TII = nullptr; member in __anoncf609d120111::R600EmitClauseMarkers
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
55 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
123 TII->getSrcs(MI); in SubstituteKCacheBank()
204 if (AluInstCount >= TII->getMaxAlusPerClause()) in canClauseLocalKillFitInClause()
238 if (AluInstCount > TII->getMaxAlusPerClause()) in MakeALUClause()
261 if (TII->mustBeLastInClause(I->getOpcode())) { in MakeALUClause()
[all …]
H A DR600ClauseMergePass.cpp39 const R600InstrInfo *TII; member in __anon8fa5ddb50111::R600ClauseMergePass
115 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
141 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
170 RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode())); in mergeIfPossible()
179 TII = ST.getInstrInfo(); in runOnMachineFunction()
186 if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) || in runOnMachineFunction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp33 const LoongArchInstrInfo *TII; member in __anon59626fc30111::LoongArchExpandAtomicPseudo
66 TII = in runOnMachineFunction()
213 BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQZ)) in doAtomicBinOpExpansion()
233 BuildMI(MBB, DL, TII->get(LoongArch::XOR), DestReg) in insertMaskedMerge()
295 BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQZ)) in doMaskedAtomicBinOpExpansion()
341 BuildMI(MBB, DL, TII->get(LoongArch::SLL_W), ValReg) in insertSext()
344 BuildMI(MBB, DL, TII->get(LoongArch::SRA_W), ValReg) in insertSext()
423 BuildMI(LoopHeadMBB, DL, TII->get(LoongArch::BGE)) in expandAtomicMinMaxOp()
431 BuildMI(LoopHeadMBB, DL, TII->get(LoongArch::BGE)) in expandAtomicMinMaxOp()
453 BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQZ)) in expandAtomicMinMaxOp()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anoncd1a18c00111::MipsInstructionSelector
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
350 I.setDesc(TII.get(COPY)); in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
435 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
620 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
814 if (!MIB.constrainAllUses(TII, TRI, RBI)) in select()
[all …]
H A DMipsBranchExpansion.cpp172 const MipsInstrInfo *TII; member in __anon018c60600111::MipsBranchExpansion
304 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
343 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
357 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
473 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
537 TII->insertNop(*BalTgtMBB, Pos, DL); in expandToLongBranch()
596 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)) in expandToLongBranch()
737 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
789 return TII->SafeInForbiddenSlot(IInSlot); in handleForbiddenSlot()
812 return TII->SafeInLoadDelaySlot(IInSlot, I); in handleLoadDelaySlot()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp55 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
62 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
77 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
146 const AVRInstrInfo &TII = *STI.getInstrInfo(); in restoreStatusRegister() local
155 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)) in restoreStatusRegister()
180 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogue() local
282 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
342 MI.setDesc(TII.get(STOpc)); in fixStackStores()
359 int Amount = TII.getFrameSize(*MI); in eliminateCallFramePseudoInstr()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in emitPrologue()
271 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); in emitPrologue()
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitPrologue()
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, in emitPrologue()
321 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); in emitPrologue()
333 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
336 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
[all …]
H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
192 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertSPConstInst()
266 const XCoreInstrInfo &TII = in eliminateFrameIndex() local
312 InsertSPImmInst(II, TII, Reg, Offset); in eliminateFrameIndex()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp142 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
190 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
232 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPAdjustment() local
277 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitSPExtend() local
313 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp34 const RISCVInstrInfo *TII; member in __anonb35cb5170111::RISCVExpandAtomicPseudo
67 Size += TII->getInstSizeInBytes(MI); in getInstSizeInBytes()
77 TII = STI->getInstrInfo(); in runOnMachineFunction()
294 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
317 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
382 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doMaskedAtomicBinOpExpansion()
430 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
433 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
501 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
509 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anona5c1c60e0111::ARMInstructionSelector
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
902 I.setDesc(TII.get(NewOpc)); in select()
958 I.setDesc(TII.get(COPY)); in select()
984 I.setDesc(TII.get(ARM::MOVi)); in select()
1030 I.setDesc(TII.get(COPY)); in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
[all …]
H A DARMFrameLowering.cpp431 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
529 insertSEH(MI, TII, MIFlags); in insertSEHRange()
1277 const ARMBaseInstrInfo &TII = in emitEpilogue() local
2074 FnSize += TII.getInstSizeInBytes(MI); in EstimateFunctionSizeInBytes()
2091 const ARMBaseInstrInfo &TII = in estimateRSStackSizeLimit() local
2279 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
2870 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2886 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr()
2997 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
3214 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp99 return TII.isCopyInstr(MI); in isCopyInstr()
142 isCopyInstr(*MI, TII, UseCopyInstr); in invalidateRegister()
229 isCopyInstr(*MI, TII, UseCopyInstr); in trackCopy()
384 const TargetInstrInfo *TII = nullptr; member in __anonf5bcd53e0111::MachineCopyPropagation
516 isCopyInstr(Copy, *TII, UseCopyInstr); in eraseIfRedundant()
540 isCopyInstr(Copy, *TII, UseCopyInstr); in isBackwardPropagatableRegClassCopy()
559 isCopyInstr(Copy, *TII, UseCopyInstr); in isForwardableRegClassCopy()
763 isCopyInstr(MI, *TII, UseCopyInstr); in ForwardCopyPropagateBlock()
1031 isCopyInstr(MI, *TII, UseCopyInstr); in BackwardCopyPropagateBlock()
1283 isCopyInstr(MI, *TII, UseCopyInstr); in EliminateSpillageCopies()
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H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
206 auto *TII = MF.getSubtarget().getInstrInfo(); in runOnMachineFunction() local
238 prependRetWithPatchableExit(MF, TII, op); in runOnMachineFunction()
246 replaceRetWithPatchableRet(MF, TII, op); in runOnMachineFunction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp41 const AArch64InstrInfo *TII = nullptr; member in __anon6e480db00111::AArch64PointerAuth
70 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in BuildPACM() local
76 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ADR)) in BuildPACM()
100 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY)) in signLR()
135 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR)) in signLR()
203 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR)) in authenticateLR()
230 const AArch64InstrInfo *TII = Subtarget.getInstrInfo(); in checkAuthenticatedRegister() local
275 BuildMI(CheckBlock, DL, TII->get(AArch64::TBNZX)) in checkAuthenticatedRegister()
288 BuildMI(CheckBlock, DL, TII->get(AArch64::XPACLRI)); in checkAuthenticatedRegister()
293 BuildMI(CheckBlock, DL, TII->get(AArch64::Bcc)) in checkAuthenticatedRegister()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp50 const SPIRVInstrInfo &TII; member in __anonaa48b9b60111::SPIRVInstructionSelector
547 .constrainAllUses(TII, TRI, RBI); in selectUnOpWithSrc()
706 .constrainAllUses(TII, TRI, RBI); in selectAtomicRMW()
720 .constrainAllUses(TII, TRI, RBI); in selectFence()
963 .constrainAllUses(TII, TRI, RBI); in selectBitreverse()
1009 .constrainAllUses(TII, TRI, RBI); in selectCmp()
1116 .constrainAllUses(TII, TRI, RBI); in selectSelect()
1165 .constrainAllUses(TII, TRI, RBI); in selectIntToBool()
1171 .constrainAllUses(TII, TRI, RBI); in selectIntToBool()
1225 .constrainAllUses(TII, TRI, RBI); in selectOpUndef()
[all …]

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