56   const SIInstrInfo *TII;  member in __anon94aa25420111::GCNDPPCombine
119   if (!TII->isVOP3(Op)) {  in isShrinkable()
122   if (!TII->hasVALU32BitEncoding(Op)) {  in isShrinkable()
130   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {  in isShrinkable()
157   if (DPP32 != -1 && TII->pseudoToMCOpcode(DPP32) != -1)  in getDPPOp()
162   if (DPP64 != -1 && TII->pseudoToMCOpcode(DPP64) != -1)  in getDPPOp()
222   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in createDPPInst()
224   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in createDPPInst()
230           !(TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 &&  in createDPPInst()
231                                    TII->isVOPC(OrigOpE32)))) &&  in createDPPInst()
235                          OrigMI.getDebugLoc(), TII->get(DPPOp))  in createDPPInst()
241     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {  in createDPPInst()
245     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {  in createDPPInst()
246       if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) {  in createDPPInst()
259               TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()),  in createDPPInst()
265     } else if (TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 &&  in createDPPInst()
266                                       TII->isVOPC(OrigOpE32))) {  in createDPPInst()
277     auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers);  in createDPPInst()
289     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in createDPPInst()
292     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {  in createDPPInst()
301     auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers);  in createDPPInst()
313     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
325       if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) {  in createDPPInst()
334     auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers);  in createDPPInst()
343     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in createDPPInst()
345       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||  in createDPPInst()
346           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {  in createDPPInst()
356       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);  in createDPPInst()
360       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);  in createDPPInst()
365       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);  in createDPPInst()
372               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {  in createDPPInst()
377         if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI))  in createDPPInst()
389               TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {  in createDPPInst()
406       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);  in createDPPInst()
410       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);  in createDPPInst()
415     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
416     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
417     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
486     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in createDPPInst()
496     auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in createDPPInst()
510   auto *Imm = TII->getNamedOperand(MI, OpndName);  in hasNoImmOrEqual()
524   auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);  in combineDPPMov()
539     auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);  in combineDPPMov()
549   auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);  in combineDPPMov()
551   auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);  in combineDPPMov()
556   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);  in combineDPPMov()
560   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);  in combineDPPMov()
561   auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in combineDPPMov()
615                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
635     assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) &&  in combineDPPMov()
668           ((TII->isVOP3P(OrigOp) || TII->isVOPC(OrigOp) ||  in combineDPPMov()
669             TII->isVOP3(OrigOp)) &&  in combineDPPMov()
671           TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {  in combineDPPMov()
680     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);  in combineDPPMov()
681     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in combineDPPMov()
687     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);  in combineDPPMov()
712       if (TII->commuteInstruction(*NewMI)) {  in combineDPPMov()
754   TII = ST->getInstrInfo();  in runOnMachineFunction()
768           auto Split = TII->expandMovDPP64(MI);  in runOnMachineFunction()