Lines Matching refs:TII
292 const TargetInstrInfo &TII, in insertSEH() argument
306 report_fatal_error("No SEH Opcode for instruction " + TII.getName(Opc)); in insertSEH()
315 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
324 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
333 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
338 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
351 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
355 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
365 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
379 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
422 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags()); in insertSEH()
431 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
446 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs)) in insertSEH()
454 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
463 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
473 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
479 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
489 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
495 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
513 const ARMBaseInstrInfo &TII, unsigned MIFlags) { in insertSEHRange() argument
529 insertSEH(MI, TII, MIFlags); in insertSEHRange()
536 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
541 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
544 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
549 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
553 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
619 const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
630 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
647 const TargetInstrInfo &TII, in emitAligningInstructions() argument
669 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
674 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
684 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
689 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
699 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
741 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
775 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
780 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
782 insertSEHRange(MBB, {}, MBBI, TII, MachineInstr::FrameSetup); in emitPrologue()
783 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
882 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, in emitPrologue()
939 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, in emitPrologue()
979 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
987 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
991 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4) in emitPrologue()
1004 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
1011 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
1015 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
1024 Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
1031 SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc)) in emitPrologue()
1046 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
1079 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII, in emitPrologue()
1082 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII, in emitPrologue()
1091 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1098 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1111 insertSEHRange(MBB, {}, End, TII, MachineInstr::FrameSetup); in emitPrologue()
1112 BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
1146 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1171 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1193 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1205 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
1225 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
1235 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
1238 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
1240 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
1255 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
1260 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
1277 const ARMBaseInstrInfo &TII = in emitEpilogue() local
1305 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1311 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1326 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1346 ARMCC::AL, 0, TII, in emitEpilogue()
1359 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy); in emitEpilogue()
1360 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1368 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
1374 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1381 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes, in emitEpilogue()
1398 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(), in emitEpilogue()
1409 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1423 insertSEHRange(MBB, RangeStart, MBB.end(), TII, MachineInstr::FrameDestroy); in emitEpilogue()
1424 BuildMI(MBB, MBB.end(), dl, TII.get(ARM::SEH_EpilogEnd)) in emitEpilogue()
1529 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPushInst() local
1574 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1581 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1606 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPopInst() local
1668 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1687 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) in emitPopInst()
1720 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Spills() local
1759 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1771 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1778 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1794 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1813 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1828 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1841 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1893 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Restores() local
1912 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1925 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1943 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1956 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1966 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
2070 const ARMBaseInstrInfo &TII) { in EstimateFunctionSizeInBytes() argument
2074 FnSize += TII.getInstSizeInBytes(MI); in EstimateFunctionSizeInBytes()
2091 const ARMBaseInstrInfo &TII = in estimateRSStackSizeLimit() local
2115 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit()
2279 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
2409 unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII); in determineCalleeSaves()
2870 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2876 bool IsDestroy = Opc == TII.getCallFrameDestroyOpcode(); in eliminateCallFramePseudoInstr()
2886 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr()
2896 unsigned Amount = TII.getFrameSize(*I); in eliminateCallFramePseudoInstr()
2904 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2908 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2915 emitSPUpdate(isARM, MBB, I, dl, TII, -CalleePopAmount, in eliminateCallFramePseudoInstr()
2997 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
3079 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3084 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3096 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3100 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3104 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3110 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
3114 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
3123 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
3130 BuildMI(McrMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3138 BuildMI(McrMBB, DL, TII.get(ARM::tSUBrr), ScratchReg1) in adjustForSegmentedStacks()
3146 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
3156 BuildMI(McrMBB, DL, TII.get(ARM::SUBrr), ScratchReg1) in adjustForSegmentedStacks()
3166 BuildMI(GetMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3176 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
3182 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
3189 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), in adjustForSegmentedStacks()
3204 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), in adjustForSegmentedStacks()
3214 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
3221 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
3234 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
3240 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3251 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
3267 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
3273 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg1) in adjustForSegmentedStacks()
3285 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
3300 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3304 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3315 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3319 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3325 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
3329 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
3336 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3339 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
3343 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
3351 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3363 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3368 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3379 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3384 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL)); in adjustForSegmentedStacks()
3389 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3394 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3405 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3412 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3416 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()