Lines Matching refs:TII
61 const MipsInstrInfo &TII; member in __anoncd1a18c00111::MipsInstructionSelector
83 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in MipsInstructionSelector()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
275 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
281 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedLoad()
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
305 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select()
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
329 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) in select()
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
335 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
350 I.setDesc(TII.get(COPY)); in select()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) in select()
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
378 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
386 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
397 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) in select()
403 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
408 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
413 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
415 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) in select()
422 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
435 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
481 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
518 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)) in select()
522 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI)) in select()
526 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) in select()
529 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
537 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) in select()
557 MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
561 if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) in select()
564 MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
568 if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) in select()
576 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
620 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
632 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) in select()
651 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
654 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI)) in select()
657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
660 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) in select()
669 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
685 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) in select()
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
698 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
708 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
717 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
725 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
814 if (!MIB.constrainAllUses(TII, TRI, RBI)) in select()
872 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
881 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) in select()
885 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) in select()
888 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) in select()
893 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) in select()
900 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); in select()
909 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) in select()
913 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI)) in select()
916 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) in select()
920 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI)) in select()
931 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in select()