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Searched refs:SRL (Results 1 – 25 of 108) sorted by relevance

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/freebsd-14.2/crypto/openssl/crypto/sha/asm/
H A Dsha512-mips.pl216 $SRL $h,$e,@Sigma1[0]
220 $SRL $tmp0,$e,@Sigma1[1]
224 $SRL $tmp0,$e,@Sigma1[2]
231 $SRL $h,$a,@Sigma0[0]
236 $SRL $tmp0,$a,@Sigma0[1]
240 $SRL $tmp0,$a,@Sigma0[2]
273 $SRL $tmp3,@X[14],@sigma1[0]
283 $SRL $tmp0,@X[1],@sigma0[1]
287 $SRL $tmp0,@X[1],@sigma0[2]
290 $SRL $tmp3,@X[14],@sigma1[0]
[all …]
H A Dsha512-sparcv9.pl70 $SRL="srlx"; # shift right logical
96 $SRL="srl"; # shift right logical
234 $SRL $e,@Sigma1[0],$h !! $i
238 $SRL $e,@Sigma1[1],$tmp0
242 $SRL $e,@Sigma1[2],$tmp0
249 $SRL $a,@Sigma0[0],$h
254 $SRL $a,@Sigma0[1],$tmp0
258 $SRL $a,@Sigma0[2],$tmp0
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h35 SRL = 0x27, enumerator
93 case SRL: in lanaiAluCodeToString()
112 .Case("srl", SRL) in stringToLanaiAluCode()
H A DLanaiISelDAGToDAG.cpp236 case ISD::SRL: in isdToLanaiAluCode()
237 return AluCode::SRL; in isdToLanaiAluCode()
H A DLanaiMemAluCombiner.cpp221 return LPAC::SRL; in mergedAluCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp858 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
861 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
864 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
982 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
985 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
988 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
991 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
995 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
998 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1001 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
[all …]
H A DX86ISelDAGToDAG.cpp752 case ISD::SRL: in IsProfitableToFold()
1151 case ISD::SRL: { in PreprocessISelDAG()
1162 case ISD::SRL: NewOpc = X86ISD::VSRLV; break; in PreprocessISelDAG()
1991 if (Shift.getOpcode() != ISD::SRL || in foldMaskAndShiftToExtract()
2223 if (Shift.getOpcode() != ISD::SRL || in foldMaskedShiftToBEXTR()
2486 case ISD::SRL: { in matchAddressRecursively()
2644 if (N.getOperand(0).getOpcode() == ISD::SRL) { in matchAddressRecursively()
3722 Node->getOpcode() == ISD::SRL) && in matchBitExtract()
3870 if (Node->getOpcode() != ISD::SRL) in matchBitExtract()
3989 if (X.getOpcode() == ISD::SRL) { in matchBitExtract()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1024 case ISD::SRL: { in combineShiftToAVG()
1737 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1746 Opc = ISD::SRL; in SimplifyDemandedBits()
1897 case ISD::SRL: { in SimplifyDemandedBits()
1922 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
2554 case ISD::SRL: in SimplifyDemandedBits()
3561 case ISD::SRL: in SimplifyDemandedVectorElts()
4126 NewShiftOpcode = ISD::SRL; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4128 case ISD::SRL: in optimizeSetCCByHoistingAndByConstFromLogicalShift()
8688 return DAG.getNode(ISD::SRL, dl, VT, in expandCTPOP()
[all …]
H A DLegalizeIntegerTypes.cpp107 case ISD::SRL: in PromoteIntegerResult()
567 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
991 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1828 case ISD::SRL: in PromoteIntegerOperand()
2850 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
2854 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
2933 case ISD::SRL: in ExpandShiftWithKnownAmountBit()
2958 case ISD::SRL: in ExpandShiftWithKnownAmountBit()
3026 case ISD::SRL: in ExpandShiftWithUnknownAmountBit()
4542 } else if (N->getOpcode() == ISD::SRL) { in ExpandIntRes_Shift()
[all …]
H A DDAGCombiner.cpp1682 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
2120 case ISD::SRL: in combine()
5186 hasOperation(ISD::SRL, VT)) { in visitMULHU()
6724 InnerShift = ISD::SRL; in unfoldExtremeBitClearingToShifts()
7532 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
14254 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
14255 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; in reduceLoadWidth() local
14261 if (!SRL.hasOneUse()) in reduceLoadWidth()
14315 N0 = SRL.getOperand(0); in reduceLoadWidth()
17938 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
[all …]
H A DLegalizeVectorOps.cpp361 case ISD::SRL: in LegalizeOp()
1351 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBSWAP()
1389 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
1406 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1607 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) { in ExpandUINT_TO_FLOAT()
1634 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord); in ExpandUINT_TO_FLOAT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp87 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
90 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
312 case ISD::SRL: { in LowerShifts()
326 case ISD::SRL: in LowerShifts()
346 case ISD::SRL: in LowerShifts()
384 case ISD::SRL: in LowerShifts()
486 case ISD::SRL: in LowerShifts()
503 case ISD::SRL: in LowerShifts()
529 case ISD::SRL: in LowerShifts()
1000 case ISD::SRL: in LowerOperation()
[all …]
/freebsd-14.2/crypto/openssl/crypto/bn/asm/
H A Dmips.pl69 $SRL="dsrl";
84 $SRL="srl";
930 $SRL $at,$a1,$t1
945 $SRL $DH,$a2,4*$BNSZ # bits
954 $SRL $HH,$a0,4*$BNSZ # bits
955 $SRL $QT,4*$BNSZ # q=0xffffffff
962 $SRL $at,$a1,4*$BNSZ # bits
987 $SRL $HH,$a0,4*$BNSZ # bits
988 $SRL $QT,4*$BNSZ # q=0xffffffff
995 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h133 R_TYPE_INST(SRL);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp126 setOperationAction(ISD::SRL, MVT::i32, Custom); in LoongArchTargetLowering()
261 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
307 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
334 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
1571 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in lowerShiftLeftParts()
1612 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
1621 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
1650 case ISD::SRL: in getLoongArchWOpcode()
1821 case ISD::SRL: in ReplaceNodeResults()
2120 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def103 ADD_BINARY_VVP_OP(VVP_SRL,VP_LSHR,SRL) REGISTER_PACKED(VVP_SRL)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp800 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
1204 N->getOperand(0).getOpcode() == ISD::SRL) || in shouldFoldConstantShiftPairToMask()
1205 (N->getOpcode() == ISD::SRL && in shouldFoldConstantShiftPairToMask()
2413 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
2414 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2460 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
2494 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in lowerFABS64()
2602 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2646 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, in lowerShiftRightParts()
2747 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h707 SRL, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp242 case LPAC::SRL: in getRrMemoryOpValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
80 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
343 case ISD::SRL: in LowerOperation()
984 case ISD::SRL: in LowerShifts()
996 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp642 case ISD::SRL: in getShiftTypeForNode()
761 if (LHSOpcode == ISD::SRL) in SelectShiftedRegisterFromAnd()
2340 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) { in isBitfieldExtractOpFromAnd()
2396 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2428 if (N->getOpcode() != ISD::SRL) in isSeveralBitsExtractOpFromShr()
2474 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL && in isBitfieldExtractOpFromShr()
2557 case ISD::SRL: in isBitfieldExtractOp()
3238 if (isOpcWithIntImmediate(Dst.getNode(), ISD::SRL, SrlImm)) { in isWorthFoldingIntoOrrWithShift()
3497 isOpcWithIntImmediate(Src.getNode(), ISD::SRL, LsrImm) && in tryBitfieldInsertOpFromOr()
3585 case ISD::SRL: in tryShiftAmountMod()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp569 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
991 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
1002 N->use_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
3492 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3496 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3505 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3545 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
4116 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) { in performTruncateCombine()
4142 (Src.getOpcode() == ISD::SRL || in performTruncateCombine()
5065 case ISD::SRL: { in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp369 TwoOperandOpcode == SystemZ::SRL || in processBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp688 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
914 Op0.getOperand(0).getOpcode() == ISD::SRL) { in tryBitfieldInsert()
924 Op1.getOperand(0).getOpcode() != ISD::SRL) { in tryBitfieldInsert()
1670 case ISD::SRL: in getValueBits()
1671 case PPCISD::SRL: in getValueBits()
4105 case ISD::SRL: in tryBitPermutation()
5155 if (Op0.getOpcode() == ISD::SRL && in tryAsSingleRLDICL()
5175 if (Val.getOpcode() == ISD::SRL && in tryAsSingleRLDICL()
5758 case ISD::SRL: { in Select()
6414 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL && in combineToCMPB()
[all …]

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