Lines Matching refs:SRL
1682 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1973 case ISD::SRL: return visitSRL(N); in visit()
2120 case ISD::SRL: in combine()
2548 BinOpcode == ISD::SRL) && Sel.hasOneUse()) { in foldBinOpIntoSelect()
2675 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2697 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit()
3849 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) { in visitSUB()
3852 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
4112 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) { in visitSUB()
4845 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike()
4951 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitUDIVLike()
4967 return DAG.getNode(ISD::SRL, DL, VT, N0, Add); in visitUDIVLike()
5039 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) && in visitREM()
5137 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
5186 hasOperation(ISD::SRL, VT)) { in visitMULHU()
5193 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc); in visitMULHU()
5208 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
5249 return DAG.getNode(ISD::SRL, DL, VT, N0, DAG.getConstant(1, DL, VT)); in visitAVG()
5388 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
5442 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
5828 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL || in hoistLogicOpWithSameOpcodeHands()
6379 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
6724 InnerShift = ISD::SRL; in unfoldExtremeBitClearingToShifts()
6725 else if (OuterShift == ISD::SRL) in unfoldExtremeBitClearingToShifts()
6784 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse()) in combineShiftAnd1ToBitTest()
6878 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL || in foldLogicOfShifts()
7379 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
7406 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
7408 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
7474 Res = DAG.getNode(ISD::SRL, DL, VT, Res, in MatchBSwapHWordLow()
7492 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
7497 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
7518 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
7532 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
7577 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) { in isBSwapHWordPair()
7613 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
7696 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt)); in MatchBSwapHWord()
7825 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
8029 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in matchRotateHalf()
8064 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL) in extractShiftForRotate()
8078 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst && in extractShiftForRotate()
8103 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) && in extractShiftForRotate()
8104 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV))) in extractShiftForRotate()
8360 if (IsBinOpImm(N1, ISD::SRL, 1) && in MatchFunnelPosNeg()
8475 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL) in MatchRotate()
8496 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt); in MatchRotate()
8545 SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt); in MatchRotate()
8943 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) && in mergeTruncStores()
9718 BinOpLHSVal.getOpcode() == ISD::SRL) && in visitShiftByConstant()
9974 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
9996 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) { in visitSHL()
10030 if (N0.getOpcode() == ISD::SRL && in visitSHL()
10040 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff); in visitSHL()
10041 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSHL()
10149 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && in combineShiftToMULH()
10180 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) { in combineShiftToMULH()
10387 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, in visitSRA()
10454 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
10481 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); in visitSRA()
10510 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, {N0, N1})) in visitSRL()
10528 if (N0.getOpcode() == ISD::SRL) { in visitSRL()
10549 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum); in visitSRL()
10554 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSRL()
10570 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
10580 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL()
10610 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01); in visitSRL()
10622 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1); in visitSRL()
10623 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff); in visitSRL()
10637 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
10640 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
10657 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); in visitSRL()
10687 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in visitSRL()
10703 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); in visitSRL()
10802 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, in visitFunnelShift()
10857 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, N2); in visitFunnelShift()
11061 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitBSWAP()
11067 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL; in visitBSWAP()
12535 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) && in visitSETCC()
12606 if (NewShiftOpc == ISD::SHL || NewShiftOpc == ISD::SRL) { in visitSETCC()
13003 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) || in CombineZExtLogicopShiftLoad()
13239 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
13877 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
14201 } else if (Opc == ISD::SRL || Opc == ISD::SRA) { in reduceLoadWidth()
14219 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD; in reduceLoadWidth()
14254 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) { in reduceLoadWidth()
14255 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0; in reduceLoadWidth() local
14261 if (!SRL.hasOneUse()) in reduceLoadWidth()
14266 auto *LN = dyn_cast<LoadSDNode>(SRL.getOperand(0)); in reduceLoadWidth()
14267 auto *SRL1C = dyn_cast<ConstantSDNode>(SRL.getOperand(1)); in reduceLoadWidth()
14301 SDNode *Mask = *(SRL->use_begin()); in reduceLoadWidth()
14302 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND && in reduceLoadWidth()
14310 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) in reduceLoadWidth()
14315 N0 = SRL.getOperand(0); in reduceLoadWidth()
14494 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
15288 X = DAG.getNode(ISD::SRL, DL, in visitBITCAST()
17938 if (N.getOpcode() == ISD::SRL || in rebuildSetCC()
17941 N.getOperand(0).getOpcode() == ISD::SRL))) { in rebuildSetCC()
18680 TLI.isOperationLegal(ISD::SRL, STType)) { in ForwardStoreValueToDirectLoad()
18681 Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val, in ForwardStoreValueToDirectLoad()
19325 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
19506 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
22113 case ISD::SRL: in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22686 if (In.getOpcode() != ISD::SRL) { in reduceBuildVecTruncToBitCast()
27079 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); in foldSelectCCToShiftAnd()