Lines Matching refs:SRL
946 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && in combineShiftToAVG()
1024 case ISD::SRL: { in combineShiftToAVG()
1599 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1737 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1746 Opc = ISD::SRL; in SimplifyDemandedBits()
1777 if (InnerOp.getOpcode() == ISD::SRL && Op0.hasOneUse() && in SimplifyDemandedBits()
1897 case ISD::SRL: { in SimplifyDemandedBits()
1922 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1948 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
1950 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
1957 TLO.DAG.getNode(ISD::SRL, dl, HalfVT, NewOp, NewShiftAmt); in SimplifyDemandedBits()
1978 SDValue NewOp = TLO.DAG.getNode(ISD::SRL, dl, VT, DemandedOp0, Op1); in SimplifyDemandedBits()
2006 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2074 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
2081 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
2193 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2196 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
2289 unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL; in SimplifyDemandedBits()
2554 case ISD::SRL: in SimplifyDemandedBits()
2557 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
2582 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, NewShAmt)); in SimplifyDemandedBits()
3561 case ISD::SRL: in SimplifyDemandedVectorElts()
4126 NewShiftOpcode = ISD::SRL; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4128 case ISD::SRL: in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4391 SDValue Shift = DAG.getNode(ISD::SRL, dl, OpVT, Y, NewShAmt); in foldSetCCWithFunnelShift()
4473 if (N0.getOpcode() == ISD::SRL && (C1.isZero() || C1.isOne()) && in SimplifySetCC()
5049 DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
5059 DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
5078 DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), in SimplifySetCC()
5106 SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, in SimplifySetCC()
6258 Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, in BuildSDIV()
6280 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildSDIV()
6305 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); in BuildSDIV()
6432 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); in BuildUDIV()
6444 Y = DAG.getNode(ISD::SRL, dl, MulVT, Y, in BuildUDIV()
6466 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildUDIV()
6489 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); in BuildUDIV()
6498 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); in BuildUDIV()
7486 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL_LOHI()
7488 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); in expandMUL_LOHI()
7490 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
7544 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
7569 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
7686 DAG.getNode(ISD::SRL, dl, HiLoVT, LL, in expandDIVREMByConstant()
7691 LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH, in expandDIVREMByConstant()
7841 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandFunnelShift()
7871 X = DAG.getNode(ISD::SRL, DL, VT, X, One); in expandFunnelShift()
7891 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); in expandFunnelShift()
7910 SDValue ShY1 = DAG.getNode(ISD::SRL, DL, VT, Y, One); in expandFunnelShift()
7911 ShY = DAG.getNode(ISD::SRL, DL, VT, ShY1, InvShAmt); in expandFunnelShift()
7915 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, ShAmt); in expandFunnelShift()
7944 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandROT()
7950 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT()
7951 unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL; in expandROT()
8009 Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt); in expandShiftParts()
8065 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
8086 DAG.getNode(ISD::SRL, dl, DstVT, R, in expandFP_TO_SINT()
8219 if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || in expandUINT_TO_FP()
8242 SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift); in expandUINT_TO_FP()
8621 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in canExpandVectorCTPOP()
8654 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8660 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8666 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8680 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
8688 return DAG.getNode(ISD::SRL, dl, VT, in expandCTPOP()
8778 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandCTLZ()
8794 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp)); in expandCTLZ()
8840 ISD::SRL, DL, VT, in CTTZTableLookup()
9051 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9053 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9068 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9071 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9074 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); in expandBSWAP()
9077 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); in expandBSWAP()
9186 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(4, dl, SHVT)); in expandBITREVERSE()
9193 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(2, dl, SHVT)); in expandBITREVERSE()
9200 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp, DAG.getConstant(1, dl, SHVT)); in expandBITREVERSE()
9215 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); in expandBITREVERSE()
9336 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
9720 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
9909 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in lowerCmpEqZeroToCtlzSrl()
10136 DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS); in expandShlSat()
10340 RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS, in expandFixedPointDiv()
10488 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL, in expandMULO()
10520 DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt)); in expandMULO()