Lines Matching refs:SRL
461 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
569 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
991 N->getOpcode() == ISD::SRL) && in isDesirableToCommuteWithShift()
1002 N->use_begin()->getOpcode() == ISD::SRL)) in isDesirableToCommuteWithShift()
2168 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
3492 SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U, in LowerFP_TO_FP16()
3496 SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3505 SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
3537 SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B); in LowerFP_TO_FP16()
3545 V = DAG.getNode(ISD::SRL, DL, MVT::i32, V, in LowerFP_TO_FP16()
3560 SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH, in LowerFP_TO_FP16()
4062 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4063 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4082 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
4116 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) { in performTruncateCombine()
4142 (Src.getOpcode() == ISD::SRL || in performTruncateCombine()
5065 case ISD::SRL: { in PerformDAGCombine()
5166 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
5323 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()