Lines Matching refs:SRL
350 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
353 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
356 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
360 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
363 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
375 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. in getArithmeticInstrCost()
379 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. in getArithmeticInstrCost()
383 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
386 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
391 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
394 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
411 { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
414 { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand. in getArithmeticInstrCost()
418 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
421 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw in getArithmeticInstrCost()
425 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld in getArithmeticInstrCost()
428 { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld in getArithmeticInstrCost()
432 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq in getArithmeticInstrCost()
435 { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq in getArithmeticInstrCost()
452 { ISD::SRL, MVT::v16i8, { 2, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
455 { ISD::SRL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
459 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
462 { ISD::SRL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psrlw + split. in getArithmeticInstrCost()
466 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld. in getArithmeticInstrCost()
469 { ISD::SRL, MVT::v8i32, { 3, 6, 4, 5 } }, // psrld + split. in getArithmeticInstrCost()
473 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 1 } }, // psrlq. in getArithmeticInstrCost()
476 { ISD::SRL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split. in getArithmeticInstrCost()
495 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld. in getArithmeticInstrCost()
507 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq. in getArithmeticInstrCost()
644 { ISD::SRL, MVT::v16i8, { 3,10, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
647 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
650 { ISD::SRL, MVT::v64i8, { 4, 8, 7,10 } }, // psrlw + pand. in getArithmeticInstrCost()
654 { ISD::SRL, MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw in getArithmeticInstrCost()
666 { ISD::SRL, MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split. in getArithmeticInstrCost()
670 { ISD::SRL, MVT::v16i32, { 2, 4, 2, 3 } }, // psrld in getArithmeticInstrCost()
675 { ISD::SRL, MVT::v4i64, { 1, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
678 { ISD::SRL, MVT::v8i64, { 1, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
691 { ISD::SRL, MVT::v16i8, { 3, 9, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
694 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
698 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
701 { ISD::SRL, MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw. in getArithmeticInstrCost()
705 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 2 } }, // psrld in getArithmeticInstrCost()
708 { ISD::SRL, MVT::v8i32, { 2, 4, 2, 3 } }, // psrld in getArithmeticInstrCost()
712 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 2 } }, // psrlq in getArithmeticInstrCost()
715 { ISD::SRL, MVT::v4i64, { 2, 4, 1, 2 } }, // psrlq in getArithmeticInstrCost()
727 { ISD::SRL, MVT::v16i8, { 4, 8, 5, 8 } }, // psrlw + pand. in getArithmeticInstrCost()
730 { ISD::SRL, MVT::v32i8, { 7, 9,10,14 } }, // psrlw + pand + split. in getArithmeticInstrCost()
734 { ISD::SRL, MVT::v8i16, { 1, 3, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
737 { ISD::SRL, MVT::v16i16, { 3, 7, 5, 7 } }, // psrlw + split. in getArithmeticInstrCost()
741 { ISD::SRL, MVT::v4i32, { 1, 3, 1, 2 } }, // psrld. in getArithmeticInstrCost()
744 { ISD::SRL, MVT::v8i32, { 3, 7, 5, 7 } }, // psrld + split. in getArithmeticInstrCost()
748 { ISD::SRL, MVT::v2i64, { 1, 3, 1, 2 } }, // psrlq. in getArithmeticInstrCost()
751 { ISD::SRL, MVT::v4i64, { 3, 7, 4, 6 } }, // psrlq + split. in getArithmeticInstrCost()
766 { ISD::SRL, MVT::v16i8, { 9, 13, 5, 9 } }, // psrlw + pand. in getArithmeticInstrCost()
770 { ISD::SRL, MVT::v8i16, { 2, 2, 1, 2 } }, // psrlw. in getArithmeticInstrCost()
774 { ISD::SRL, MVT::v4i32, { 2, 2, 1, 2 } }, // psrld. in getArithmeticInstrCost()
778 { ISD::SRL, MVT::v2i64, { 2, 2, 1, 2 } }, // psrlq. in getArithmeticInstrCost()
803 { ISD::SRL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
806 { ISD::SRL, MVT::v32i8, { 4, 30,12,18 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
809 { ISD::SRL, MVT::v64i8, { 7, 27,15,18 } }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
813 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
816 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
819 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsrlvw in getArithmeticInstrCost()
850 { ISD::SRL, MVT::v64i8, { 15, 19,30,36 } }, // vpblendv+split sequence. in getArithmeticInstrCost()
854 { ISD::SRL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
858 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
861 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
864 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
868 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
871 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
874 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
946 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org) in getArithmeticInstrCost()
949 { ISD::SRL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org) in getArithmeticInstrCost()
952 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org) in getArithmeticInstrCost()
954 { ISD::SRL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org) in getArithmeticInstrCost()
982 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
985 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
988 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
991 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, in getArithmeticInstrCost()
995 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
998 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1001 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1004 { ISD::SRL, MVT::v4i64, { 6, 7, 5, 6 } }, in getArithmeticInstrCost()
1013 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant()) in getArithmeticInstrCost()
1077 { ISD::SRL, MVT::v16i8, { 6, 27,12,18 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1078 { ISD::SRL, MVT::v32i8, { 8, 30,12,24 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1079 { ISD::SRL, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1080 { ISD::SRL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1191 { ISD::SRL, MVT::v16i8, { 11, 27,12,18 } }, // pblendvb sequence. in getArithmeticInstrCost()
1192 { ISD::SRL, MVT::v32i8, { 23, 23,30,43 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1193 { ISD::SRL, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence. in getArithmeticInstrCost()
1194 { ISD::SRL, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1195 { ISD::SRL, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1196 { ISD::SRL, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split. in getArithmeticInstrCost()
1197 { ISD::SRL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1198 { ISD::SRL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split. in getArithmeticInstrCost()
1280 { ISD::SRL, MVT::v16i8, { 16, 27,18,24 } }, // pblendvb sequence. in getArithmeticInstrCost()
1281 { ISD::SRL, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence. in getArithmeticInstrCost()
1282 { ISD::SRL, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1283 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence. in getArithmeticInstrCost()
1307 { ISD::SRL, MVT::v16i8, { 14, 28,27,30 } }, // cmpgtb sequence. in getArithmeticInstrCost()
1308 { ISD::SRL, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence. in getArithmeticInstrCost()
1309 { ISD::SRL, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1310 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence. in getArithmeticInstrCost()