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Searched refs:RegVT (Results 1 – 22 of 22) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1717 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1729 if (RegVT == MVT::i8) in LowerFormalArguments()
1731 else if (RegVT == MVT::i16) in LowerFormalArguments()
1733 else if (RegVT == MVT::i32) in LowerFormalArguments()
1737 else if (RegVT == MVT::f16) in LowerFormalArguments()
1739 else if (RegVT == MVT::f32) in LowerFormalArguments()
1741 else if (RegVT == MVT::f64) in LowerFormalArguments()
1743 else if (RegVT == MVT::f80) in LowerFormalArguments()
1745 else if (RegVT == MVT::f128) in LowerFormalArguments()
1755 else if (RegVT == MVT::v1i1) in LowerFormalArguments()
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H A DX86ISelLowering.cpp24547 MVT RegVT = Op.getSimpleValueType(); in LowerLoad() local
24549 assert(RegVT.isInteger() && in LowerLoad()
24556 if (RegVT.getVectorElementType() == MVT::i1) { in LowerLoad()
24570 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, in LowerLoad()
49956 EVT RegVT = Ld->getValueType(0); in combineLoad() local
49973 unsigned NumElems = RegVT.getVectorNumElements(); in combineLoad()
50002 unsigned NumElts = RegVT.getVectorNumElements(); in combineLoad()
50009 SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad); in combineLoad()
50017 (RegVT.is128BitVector() || RegVT.is256BitVector())) { in combineLoad()
50028 RegVT.getFixedSizeInBits()) { in combineLoad()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp249 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
251 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
256 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp350 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
351 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
357 RegVT.print(OS); in LowerFormalArguments()
366 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
371 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
374 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h217 MVT RegVT; member
231 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp523 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
533 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1409 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1411 if (RegVT == MVT::i8) { in LowerFormalArguments()
1413 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1420 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1437 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1442 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1542 EVT RegVT = VA.getLocVT(); in LowerCall() local
1552 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1555 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1558 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp458 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
459 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
463 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
469 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
472 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
483 << RegVT << "\n"); in LowerCCCArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp643 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
644 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
649 << RegVT << "\n"; in LowerCCCArguments()
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp646 EVT RegVT = VA.getLocVT(); in LowerCall() local
657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
666 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
946 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
948 if (RegVT == MVT::i32) in LowerFormalArguments()
954 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
960 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
963 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp838 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
840 RegVT = VA.getValVT(); in LowerFormalArguments()
842 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
844 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
850 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
851 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
852 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
853 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
857 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
859 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1209 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1210 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1215 << RegVT << "\n"; in LowerCCCArguments()
1222 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1005 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local
1006 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
H A DIRTranslator.cpp1118 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader()
1150 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3036 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
3037 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
3075 MVT VT = BB.RegVT; in visitBitTestCase()
9108 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in getRegistersForValue() local
9131 OpInfo.ConstraintVT = RegVT; in getRegistersForValue()
9152 ValueVT = RegVT; in getRegistersForValue()
9185 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in getRegistersForValue()
9518 MVT RegVT = R->getSimpleValueType(0); in visitInlineAsm() local
9521 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
11131 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local
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H A DTargetLowering.cpp9391 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
9392 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
9489 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
9491 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
9495 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
9529 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
9639 MVT RegVT = getRegisterType( in expandUnalignedStore() local
9644 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
9648 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
9667 RegVT, dl, Store, StackPtr, in expandUnalignedStore()
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H A DLegalizeIntegerTypes.cpp1717 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1723 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1739 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3690 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3692 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3697 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3704 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3705 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3706 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3708 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3714 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5544 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5548 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5554 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5556 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5561 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5563 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5596 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5619 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5629 RegVT)); in buildCallOperands()
6737 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX() local
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H A DPPCISelDAGToDAG.cpp796 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
803 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
807 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
811 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
844 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
851 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
855 if (RegVT == MVT::i32) in tryTLSXFormLoad()
862 if (RegVT == MVT::i32) in tryTLSXFormLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3097 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
3102 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) { in IsEligibleForTailCallOptimization()
3111 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
4543 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4571 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
4573 else if (RegVT == MVT::f32) in LowerFormalArguments()
4575 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments()
4576 RegVT == MVT::v4bf16) in LowerFormalArguments()
4578 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments()
4579 RegVT == MVT::v8bf16) in LowerFormalArguments()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp6717 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
6720 if (RegVT == MVT::i32) in LowerFormalArguments()
6722 else if (RegVT == MVT::i64) in LowerFormalArguments()
6724 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
6726 else if (RegVT == MVT::f32) in LowerFormalArguments()
6728 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6730 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
6732 else if (RegVT.isScalableVector() && in LowerFormalArguments()
6733 RegVT.getVectorElementType() == MVT::i1) { in LowerFormalArguments()
6736 } else if (RegVT == MVT::aarch64svcount) { in LowerFormalArguments()
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