1717       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
1729         if (RegVT == MVT::i8)  in LowerFormalArguments()
1731         else if (RegVT == MVT::i16)  in LowerFormalArguments()
1733         else if (RegVT == MVT::i32)  in LowerFormalArguments()
1735         else if (Is64Bit && RegVT == MVT::i64)  in LowerFormalArguments()
1737         else if (RegVT == MVT::f16)  in LowerFormalArguments()
1739         else if (RegVT == MVT::f32)  in LowerFormalArguments()
1741         else if (RegVT == MVT::f64)  in LowerFormalArguments()
1743         else if (RegVT == MVT::f80)  in LowerFormalArguments()
1745         else if (RegVT == MVT::f128)  in LowerFormalArguments()
1747         else if (RegVT.is512BitVector())  in LowerFormalArguments()
1749         else if (RegVT.is256BitVector())  in LowerFormalArguments()
1751         else if (RegVT.is128BitVector())  in LowerFormalArguments()
1753         else if (RegVT == MVT::x86mmx)  in LowerFormalArguments()
1755         else if (RegVT == MVT::v1i1)  in LowerFormalArguments()
1757         else if (RegVT == MVT::v8i1)  in LowerFormalArguments()
1759         else if (RegVT == MVT::v16i1)  in LowerFormalArguments()
1761         else if (RegVT == MVT::v32i1)  in LowerFormalArguments()
1763         else if (RegVT == MVT::v64i1)  in LowerFormalArguments()
1769         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);  in LowerFormalArguments()
1776         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,  in LowerFormalArguments()
1779         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,  in LowerFormalArguments()
1786         if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)  in LowerFormalArguments()
1793           ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);  in LowerFormalArguments()
2149     EVT RegVT = VA.getLocVT();  in LowerCall()  local
2158       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
2161       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);  in LowerCall()
2166         Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);  in LowerCall()
2167       else if (RegVT.is128BitVector()) {  in LowerCall()
2173         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);  in LowerCall()
2176       Arg = DAG.getBitcast(RegVT, Arg);  in LowerCall()