Lines Matching refs:RegVT
1409 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1411 if (RegVT == MVT::i8) { in LowerFormalArguments()
1413 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1420 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1437 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1442 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1542 EVT RegVT = VA.getLocVT(); in LowerCall() local
1552 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1555 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1558 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1561 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()