Lines Matching refs:RegVT
3036 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
3037 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
3075 MVT VT = BB.RegVT; in visitBitTestCase()
9108 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in getRegistersForValue() local
9110 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in getRegistersForValue()
9124 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in getRegistersForValue()
9130 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in getRegistersForValue()
9131 OpInfo.ConstraintVT = RegVT; in getRegistersForValue()
9135 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in getRegistersForValue()
9152 ValueVT = RegVT; in getRegistersForValue()
9157 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT, RegVT); in getRegistersForValue()
9185 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in getRegistersForValue()
9518 MVT RegVT = R->getSimpleValueType(0); in visitInlineAsm() local
9521 : RegVT != MVT::Untyped ? TLI.getRegClassFor(RegVT) in visitInlineAsm()
9526 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); in visitInlineAsm()
11131 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local
11134 getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, nullptr, NewRoot, in LowerArguments()
11140 RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()