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Searched refs:CSR_WRITE_2 (Results 1 – 25 of 39) sorted by relevance

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/freebsd-14.2/sys/dev/xl/
H A Dif_xl.c406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); in xl_mii_bitbang_write()
571 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
574 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
2117 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc()
2120 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc()
2157 CSR_WRITE_2(sc, XL_COMMAND, in xl_intr()
2243 CSR_WRITE_2(sc, XL_COMMAND, in xl_poll_locked()
2700 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); in xl_init_locked()
2761 CSR_WRITE_2(sc, XL_COMMAND, in xl_init_locked()
3049 CSR_WRITE_2(sc, XL_COMMAND, in xl_ioctl()
[all …]
H A Dif_xlreg.h654 #define CSR_WRITE_2(sc, reg, val) \ macro
672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
/freebsd-14.2/sys/dev/vte/
H A Dif_vte.c200 CSR_WRITE_2(sc, VTE_MMWD, val); in vte_miibus_writereg()
257 CSR_WRITE_2(sc, VTE_MRICR, val); in vte_miibus_statchg()
265 CSR_WRITE_2(sc, VTE_MTICR, val); in vte_miibus_statchg()
1248 CSR_WRITE_2(sc, VTE_MCR0, mcr); in vte_mac_config()
1349 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_intr()
1616 CSR_WRITE_2(sc, VTE_MACSM, 0); in vte_reset()
1740 CSR_WRITE_2(sc, VTE_MRICR, 0); in vte_init_locked()
1741 CSR_WRITE_2(sc, VTE_MTICR, 0); in vte_init_locked()
1750 CSR_WRITE_2(sc, VTE_MISR, 0); in vte_init_locked()
1781 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_stop()
[all …]
H A Dif_vtevar.h149 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-14.2/sys/dev/bwi/
H A Dbwimac.c217 CSR_WRITE_2(sc, data_reg, v); in bwi_memobj_write_2()
366 CSR_WRITE_2(sc, 0x60e, 0); in bwi_mac_init()
368 CSR_WRITE_2(sc, 0x604, 0); in bwi_mac_init()
720 CSR_WRITE_2(sc, 0x568, 0); in bwi_mac_dummy_xmit()
721 CSR_WRITE_2(sc, 0x7c0, 0); in bwi_mac_dummy_xmit()
723 CSR_WRITE_2(sc, 0x508, 0); in bwi_mac_dummy_xmit()
724 CSR_WRITE_2(sc, 0x50a, 0); in bwi_mac_dummy_xmit()
725 CSR_WRITE_2(sc, 0x54c, 0); in bwi_mac_dummy_xmit()
726 CSR_WRITE_2(sc, 0x56a, 0x14); in bwi_mac_dummy_xmit()
728 CSR_WRITE_2(sc, 0x500, 0); in bwi_mac_dummy_xmit()
[all …]
H A Dbwiphy.c139 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_write()
140 CSR_WRITE_2(sc, BWI_PHY_DATA, data); in bwi_phy_write()
148 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_read()
441 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev4()
451 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev4()
488 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100); in bwi_phy_init_11b_rev4()
535 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0); in bwi_phy_init_11b_rev5()
559 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev5()
567 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev5()
728 CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2); in bwi_phy_init_11b_rev6()
[all …]
H A Dbwirf.c201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_write()
202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data); in bwi_rf_write()
220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_read()
786 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f); in bwi_rf_init_bcm2050()
824 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); in bwi_rf_init_bcm2050()
1311 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0); in bwi_rf_lo_update_11g()
1374 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div); in bwi_rf_lo_update_11g()
1675 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f); in bwi_rf_calc_nrssi_slope_11b()
1689 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40); in bwi_rf_calc_nrssi_slope_11b()
1691 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122); in bwi_rf_calc_nrssi_slope_11b()
[all …]
H A Dif_bwivar.h83 #define CSR_WRITE_2(sc, reg, val) \ macro
89 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
94 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
99 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
/freebsd-14.2/sys/dev/ste/
H A Dif_ste.c296 CSR_WRITE_2(sc, STE_MACCTL0, cfg); in ste_miibus_statchg()
552 CSR_WRITE_2(sc, STE_COUNTDOWN, in ste_intr()
579 CSR_WRITE_2(sc, STE_IMR, intrs); in ste_intr()
1517 CSR_WRITE_2(sc, STE_PAR0 + i, in ste_init_locked()
1580 CSR_WRITE_2(sc, STE_MACCTL0, 0); in ste_init_locked()
1581 CSR_WRITE_2(sc, STE_MACCTL1, 0); in ste_init_locked()
1590 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); in ste_init_locked()
1591 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); in ste_init_locked()
1595 CSR_WRITE_2(sc, STE_IMR, 0); in ste_init_locked()
1627 CSR_WRITE_2(sc, STE_IMR, 0); in ste_stop()
[all …]
/freebsd-14.2/sys/dev/stge/
H A Dif_stge.c399 CSR_WRITE_2(sc, STGE_EepromCtrl, in stge_read_eeprom()
1308 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_ioctl()
1316 CSR_WRITE_2(sc, STGE_IntEnable, in stge_ioctl()
2087 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_init_locked()
2126 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2130 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2133 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init_locked()
2214 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_stop()
2498 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_filter()
2533 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_multi()
[all …]
/freebsd-14.2/sys/dev/vge/
H A Dif_vgevar.h219 #define CSR_WRITE_2(sc, reg, val) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vge.c405 CSR_WRITE_2(sc, VGE_MIIDATA, data); in vge_miibus_writereg()
1591 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, in vge_rxeof()
1999 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); in vge_start_locked()
2081 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); in vge_init_locked()
2085 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); in vge_init_locked()
2086 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); in vge_init_locked()
2096 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); in vge_init_locked()
2106 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); in vge_init_locked()
2408 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); in vge_stop()
/freebsd-14.2/sys/dev/vr/
H A Dif_vr.c272 CSR_WRITE_2(sc, VR_MIIDATA, data); in vr_miibus_writereg()
734 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_attach()
735 CSR_WRITE_2(sc, VR_IMR, 0); in vr_attach()
737 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_attach()
1677 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_intr()
1708 CSR_WRITE_2(sc, VR_IMR, 0); in vr_int_task()
1756 CSR_WRITE_2(sc, VR_IMR, 0); in vr_error()
2143 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_init_locked()
2149 CSR_WRITE_2(sc, VR_IMR, 0); in vr_init_locked()
2157 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_init_locked()
[all …]
H A Dif_vrreg.h750 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) macro
759 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
760 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-14.2/sys/dev/rl/
H A Dif_rl.c466 CSR_WRITE_2(sc, rl8139_reg, data); in rl_miibus_writereg()
1208 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
1465 CSR_WRITE_2(sc, RL_ISR, status); in rl_poll_locked()
1504 CSR_WRITE_2(sc, RL_IMR, 0); in rl_intr()
1506 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr()
1530 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
1741 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init_locked()
1745 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init_locked()
1847 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_ioctl()
1858 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_ioctl()
[all …]
H A Dif_rlreg.h949 #define CSR_WRITE_2(sc, reg, val) \ macro
971 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
974 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-14.2/sys/dev/re/
H A Dif_re.c612 CSR_WRITE_2(sc, re8139_reg, data); in re_miibus_writereg()
839 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); in re_diag()
851 CSR_WRITE_2(sc, RL_ISR, status); in re_diag()
2570 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
2665 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr_msi()
2723 CSR_WRITE_2(sc, RL_IMR, intrs); in re_intr_msi()
3178 CSR_WRITE_2(sc, 0xe2, 0); in re_init_locked()
3267 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3275 CSR_WRITE_2(sc, RL_IMR, 0); in re_init_locked()
3658 CSR_WRITE_2(sc, RL_IMR, 0x0000); in re_stop()
[all …]
/freebsd-14.2/sys/dev/msk/
H A Dif_msk.c685 CSR_WRITE_2(sc_if->msk_softc, in msk_rx_fill()
750 CSR_WRITE_2(sc_if->msk_softc, in msk_init_rx_ring()
818 CSR_WRITE_2(sc_if->msk_softc, in msk_init_jumbo_rx_ring()
1374 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_reset()
1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_reset()
1385 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); in mskc_reset()
1772 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_attach()
2082 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_detach()
2942 CSR_WRITE_2(sc_if->msk_softc, in msk_start_locked()
2996 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_shutdown()
[all …]
/freebsd-14.2/sys/dev/fxp/
H A Dif_fxp.c1138 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1142 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_getword()
1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1197 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1200 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_getword()
1217 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
1226 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
1238 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
[all …]
H A Dif_fxpvar.h248 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
/freebsd-14.2/sys/dev/ipw/
H A Dif_ipwreg.h338 #define CSR_WRITE_2(sc, reg, val) \ macro
366 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-14.2/sys/dev/iwi/
H A Dif_iwireg.h588 #define CSR_WRITE_2(sc, reg, val) \ macro
608 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-14.2/sys/dev/ale/
H A Dif_alevar.h231 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-14.2/sys/dev/sk/
H A Dif_sk.c410 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); in sk_win_write_2()
412 CSR_WRITE_2(sc, reg, val); in sk_win_write_2()
1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); in sk_reset()
1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); in sk_reset()
1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); in sk_reset()
1166 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); in sk_reset()
1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); in sk_reset()
1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); in sk_reset()
1717 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); in skc_attach()
2491 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); in skc_shutdown()
/freebsd-14.2/sys/dev/age/
H A Dif_agevar.h239 #define CSR_WRITE_2(_sc, reg, val) \ macro

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