189 	CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192 	CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
296 		CSR_WRITE_2(sc, STE_MACCTL0, cfg);  in ste_miibus_statchg()
393 		CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));  in ste_read_eeprom()
448 	CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);  in ste_rxfilter()
449 	CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);  in ste_rxfilter()
450 	CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);  in ste_rxfilter()
451 	CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);  in ste_rxfilter()
552 				CSR_WRITE_2(sc, STE_COUNTDOWN,  in ste_intr()
579 		CSR_WRITE_2(sc, STE_IMR, intrs);  in ste_intr()
727 		CSR_WRITE_2(sc, STE_TX_STATUS, txstat);  in ste_txeoc()
1517 		CSR_WRITE_2(sc, STE_PAR0 + i,  in ste_init_locked()
1546 	CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);  in ste_init_locked()
1552 	CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);  in ste_init_locked()
1580 	CSR_WRITE_2(sc, STE_MACCTL0, 0);  in ste_init_locked()
1581 	CSR_WRITE_2(sc, STE_MACCTL1, 0);  in ste_init_locked()
1590 	CSR_WRITE_2(sc, STE_COUNTDOWN, 0);  in ste_init_locked()
1591 	CSR_WRITE_2(sc, STE_ISR, 0xFFFF);  in ste_init_locked()
1595 		CSR_WRITE_2(sc, STE_IMR, 0);  in ste_init_locked()
1599 	CSR_WRITE_2(sc, STE_IMR, STE_INTRS);  in ste_init_locked()
1627 	CSR_WRITE_2(sc, STE_IMR, 0);  in ste_stop()
1628 	CSR_WRITE_2(sc, STE_COUNTDOWN, 0);  in ste_stop()
1644 	CSR_WRITE_2(sc, STE_MACCTL1, val);  in ste_stop()
1721 		CSR_WRITE_2(sc, STE_MACCTL1, mac);  in ste_restart_tx()
1784 				CSR_WRITE_2(sc, STE_IMR, 0);  in ste_ioctl()
1788 				CSR_WRITE_2(sc, STE_IMR, STE_INTRS);  in ste_ioctl()