1 /******************************************************************************
2 *
3 * Name : sky2.c
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
8 *
9 *****************************************************************************/
10
11 /******************************************************************************
12 *
13 * LICENSE:
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
15 *
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
20 * and conditions:
21 *
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 * /LICENSE
45 *
46 *****************************************************************************/
47
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
50 *
51 * Copyright (c) 1997, 1998, 1999, 2000
52 * Bill Paul <[email protected]>. All rights reserved.
53 *
54 * Redistribution and use in source and binary forms, with or without
55 * modification, are permitted provided that the following conditions
56 * are met:
57 * 1. Redistributions of source code must retain the above copyright
58 * notice, this list of conditions and the following disclaimer.
59 * 2. Redistributions in binary form must reproduce the above copyright
60 * notice, this list of conditions and the following disclaimer in the
61 * documentation and/or other materials provided with the distribution.
62 * 3. All advertising materials mentioning features or use of this software
63 * must display the following acknowledgement:
64 * This product includes software developed by Bill Paul.
65 * 4. Neither the name of the author nor the names of any co-contributors
66 * may be used to endorse or promote products derived from this software
67 * without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
79 * THE POSSIBILITY OF SUCH DAMAGE.
80 */
81 /*-
82 * Copyright (c) 2003 Nathan L. Binkert <[email protected]>
83 *
84 * Permission to use, copy, modify, and distribute this software for any
85 * purpose with or without fee is hereby granted, provided that the above
86 * copyright notice and this permission notice appear in all copies.
87 *
88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
95 */
96
97 /*
98 * Device driver for the Marvell Yukon II Ethernet controller.
99 * Due to lack of documentation, this driver is based on the code from
100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
101 */
102
103 #include <sys/cdefs.h>
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/bus.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/malloc.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/sockio.h>
114 #include <sys/queue.h>
115 #include <sys/sysctl.h>
116
117 #include <net/bpf.h>
118 #include <net/ethernet.h>
119 #include <net/if.h>
120 #include <net/if_var.h>
121 #include <net/if_arp.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
125 #include <net/if_vlan_var.h>
126
127 #include <netinet/in.h>
128 #include <netinet/in_systm.h>
129 #include <netinet/ip.h>
130 #include <netinet/tcp.h>
131 #include <netinet/udp.h>
132
133 #include <machine/bus.h>
134 #include <machine/in_cksum.h>
135 #include <machine/resource.h>
136 #include <sys/rman.h>
137
138 #include <dev/mii/mii.h>
139 #include <dev/mii/miivar.h>
140
141 #include <dev/pci/pcireg.h>
142 #include <dev/pci/pcivar.h>
143
144 #include <dev/msk/if_mskreg.h>
145
146 MODULE_DEPEND(msk, pci, 1, 1, 1);
147 MODULE_DEPEND(msk, ether, 1, 1, 1);
148 MODULE_DEPEND(msk, miibus, 1, 1, 1);
149
150 /* "device miibus" required. See GENERIC if you get errors here. */
151 #include "miibus_if.h"
152
153 /* Tunables. */
154 static int msi_disable = 0;
155 TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
156 static int legacy_intr = 0;
157 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
158 static int jumbo_disable = 0;
159 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
160
161 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
162
163 /*
164 * Devices supported by this driver.
165 */
166 static const struct msk_product {
167 uint16_t msk_vendorid;
168 uint16_t msk_deviceid;
169 const char *msk_name;
170 } msk_products[] = {
171 { VENDORID_SK, DEVICEID_SK_YUKON2,
172 "SK-9Sxx Gigabit Ethernet" },
173 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
174 "SK-9Exx Gigabit Ethernet"},
175 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
176 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
177 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
178 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
179 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
180 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
181 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
182 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
183 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
184 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
185 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
186 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
187 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
188 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
189 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
190 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
191 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
192 "Marvell Yukon 88E8035 Fast Ethernet" },
193 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
194 "Marvell Yukon 88E8036 Fast Ethernet" },
195 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
196 "Marvell Yukon 88E8038 Fast Ethernet" },
197 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
198 "Marvell Yukon 88E8039 Fast Ethernet" },
199 { VENDORID_MARVELL, DEVICEID_MRVL_8040,
200 "Marvell Yukon 88E8040 Fast Ethernet" },
201 { VENDORID_MARVELL, DEVICEID_MRVL_8040T,
202 "Marvell Yukon 88E8040T Fast Ethernet" },
203 { VENDORID_MARVELL, DEVICEID_MRVL_8042,
204 "Marvell Yukon 88E8042 Fast Ethernet" },
205 { VENDORID_MARVELL, DEVICEID_MRVL_8048,
206 "Marvell Yukon 88E8048 Fast Ethernet" },
207 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
208 "Marvell Yukon 88E8050 Gigabit Ethernet" },
209 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
210 "Marvell Yukon 88E8052 Gigabit Ethernet" },
211 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
212 "Marvell Yukon 88E8053 Gigabit Ethernet" },
213 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
214 "Marvell Yukon 88E8055 Gigabit Ethernet" },
215 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
216 "Marvell Yukon 88E8056 Gigabit Ethernet" },
217 { VENDORID_MARVELL, DEVICEID_MRVL_4365,
218 "Marvell Yukon 88E8070 Gigabit Ethernet" },
219 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
220 "Marvell Yukon 88E8058 Gigabit Ethernet" },
221 { VENDORID_MARVELL, DEVICEID_MRVL_436B,
222 "Marvell Yukon 88E8071 Gigabit Ethernet" },
223 { VENDORID_MARVELL, DEVICEID_MRVL_436C,
224 "Marvell Yukon 88E8072 Gigabit Ethernet" },
225 { VENDORID_MARVELL, DEVICEID_MRVL_436D,
226 "Marvell Yukon 88E8055 Gigabit Ethernet" },
227 { VENDORID_MARVELL, DEVICEID_MRVL_4370,
228 "Marvell Yukon 88E8075 Gigabit Ethernet" },
229 { VENDORID_MARVELL, DEVICEID_MRVL_4380,
230 "Marvell Yukon 88E8057 Gigabit Ethernet" },
231 { VENDORID_MARVELL, DEVICEID_MRVL_4381,
232 "Marvell Yukon 88E8059 Gigabit Ethernet" },
233 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
234 "D-Link 550SX Gigabit Ethernet" },
235 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
236 "D-Link 560SX Gigabit Ethernet" },
237 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
238 "D-Link 560T Gigabit Ethernet" }
239 };
240
241 static const char *model_name[] = {
242 "Yukon XL",
243 "Yukon EC Ultra",
244 "Yukon EX",
245 "Yukon EC",
246 "Yukon FE",
247 "Yukon FE+",
248 "Yukon Supreme",
249 "Yukon Ultra 2",
250 "Yukon Unknown",
251 "Yukon Optima",
252 };
253
254 static int mskc_probe(device_t);
255 static int mskc_attach(device_t);
256 static int mskc_detach(device_t);
257 static int mskc_shutdown(device_t);
258 static int mskc_setup_rambuffer(struct msk_softc *);
259 static int mskc_suspend(device_t);
260 static int mskc_resume(device_t);
261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t);
262 static void mskc_reset(struct msk_softc *);
263
264 static int msk_probe(device_t);
265 static int msk_attach(device_t);
266 static int msk_detach(device_t);
267
268 static void msk_tick(void *);
269 static void msk_intr(void *);
270 static void msk_intr_phy(struct msk_if_softc *);
271 static void msk_intr_gmac(struct msk_if_softc *);
272 static __inline void msk_rxput(struct msk_if_softc *);
273 static int msk_handle_events(struct msk_softc *);
274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
275 static void msk_intr_hwerr(struct msk_softc *);
276 #ifndef __NO_STRICT_ALIGNMENT
277 static __inline void msk_fixup_rx(struct mbuf *);
278 #endif
279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
282 static void msk_txeof(struct msk_if_softc *, int);
283 static int msk_encap(struct msk_if_softc *, struct mbuf **);
284 static void msk_start(if_t);
285 static void msk_start_locked(if_t);
286 static int msk_ioctl(if_t, u_long, caddr_t);
287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
288 static void msk_set_rambuffer(struct msk_if_softc *);
289 static void msk_set_tx_stfwd(struct msk_if_softc *);
290 static void msk_init(void *);
291 static void msk_init_locked(struct msk_if_softc *);
292 static void msk_stop(struct msk_if_softc *);
293 static void msk_watchdog(struct msk_if_softc *);
294 static int msk_mediachange(if_t);
295 static void msk_mediastatus(if_t, struct ifmediareq *);
296 static void msk_phy_power(struct msk_softc *, int);
297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
298 static int msk_status_dma_alloc(struct msk_softc *);
299 static void msk_status_dma_free(struct msk_softc *);
300 static int msk_txrx_dma_alloc(struct msk_if_softc *);
301 static int msk_rx_dma_jalloc(struct msk_if_softc *);
302 static void msk_txrx_dma_free(struct msk_if_softc *);
303 static void msk_rx_dma_jfree(struct msk_if_softc *);
304 static int msk_rx_fill(struct msk_if_softc *, int);
305 static int msk_init_rx_ring(struct msk_if_softc *);
306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
307 static void msk_init_tx_ring(struct msk_if_softc *);
308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
310 static int msk_newbuf(struct msk_if_softc *, int);
311 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
312
313 static int msk_phy_readreg(struct msk_if_softc *, int, int);
314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
315 static int msk_miibus_readreg(device_t, int, int);
316 static int msk_miibus_writereg(device_t, int, int, int);
317 static void msk_miibus_statchg(device_t);
318
319 static void msk_rxfilter(struct msk_if_softc *);
320 static void msk_setvlan(struct msk_if_softc *, if_t);
321
322 static void msk_stats_clear(struct msk_if_softc *);
323 static void msk_stats_update(struct msk_if_softc *);
324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
326 static void msk_sysctl_node(struct msk_if_softc *);
327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
329
330 static device_method_t mskc_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, mskc_probe),
333 DEVMETHOD(device_attach, mskc_attach),
334 DEVMETHOD(device_detach, mskc_detach),
335 DEVMETHOD(device_suspend, mskc_suspend),
336 DEVMETHOD(device_resume, mskc_resume),
337 DEVMETHOD(device_shutdown, mskc_shutdown),
338
339 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag),
340
341 DEVMETHOD_END
342 };
343
344 static driver_t mskc_driver = {
345 "mskc",
346 mskc_methods,
347 sizeof(struct msk_softc)
348 };
349
350 static device_method_t msk_methods[] = {
351 /* Device interface */
352 DEVMETHOD(device_probe, msk_probe),
353 DEVMETHOD(device_attach, msk_attach),
354 DEVMETHOD(device_detach, msk_detach),
355 DEVMETHOD(device_shutdown, bus_generic_shutdown),
356
357 /* MII interface */
358 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
359 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
360 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
361
362 DEVMETHOD_END
363 };
364
365 static driver_t msk_driver = {
366 "msk",
367 msk_methods,
368 sizeof(struct msk_if_softc)
369 };
370
371 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL);
372 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL);
373 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL);
374
375 static struct resource_spec msk_res_spec_io[] = {
376 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
377 { -1, 0, 0 }
378 };
379
380 static struct resource_spec msk_res_spec_mem[] = {
381 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
382 { -1, 0, 0 }
383 };
384
385 static struct resource_spec msk_irq_spec_legacy[] = {
386 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
387 { -1, 0, 0 }
388 };
389
390 static struct resource_spec msk_irq_spec_msi[] = {
391 { SYS_RES_IRQ, 1, RF_ACTIVE },
392 { -1, 0, 0 }
393 };
394
395 static int
msk_miibus_readreg(device_t dev,int phy,int reg)396 msk_miibus_readreg(device_t dev, int phy, int reg)
397 {
398 struct msk_if_softc *sc_if;
399
400 sc_if = device_get_softc(dev);
401
402 return (msk_phy_readreg(sc_if, phy, reg));
403 }
404
405 static int
msk_phy_readreg(struct msk_if_softc * sc_if,int phy,int reg)406 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
407 {
408 struct msk_softc *sc;
409 int i, val;
410
411 sc = sc_if->msk_softc;
412
413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
414 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
415
416 for (i = 0; i < MSK_TIMEOUT; i++) {
417 DELAY(1);
418 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
419 if ((val & GM_SMI_CT_RD_VAL) != 0) {
420 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
421 break;
422 }
423 }
424
425 if (i == MSK_TIMEOUT) {
426 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
427 val = 0;
428 }
429
430 return (val);
431 }
432
433 static int
msk_miibus_writereg(device_t dev,int phy,int reg,int val)434 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
435 {
436 struct msk_if_softc *sc_if;
437
438 sc_if = device_get_softc(dev);
439
440 return (msk_phy_writereg(sc_if, phy, reg, val));
441 }
442
443 static int
msk_phy_writereg(struct msk_if_softc * sc_if,int phy,int reg,int val)444 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
445 {
446 struct msk_softc *sc;
447 int i;
448
449 sc = sc_if->msk_softc;
450
451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
453 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
454 for (i = 0; i < MSK_TIMEOUT; i++) {
455 DELAY(1);
456 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
457 GM_SMI_CT_BUSY) == 0)
458 break;
459 }
460 if (i == MSK_TIMEOUT)
461 if_printf(sc_if->msk_ifp, "phy write timeout\n");
462
463 return (0);
464 }
465
466 static void
msk_miibus_statchg(device_t dev)467 msk_miibus_statchg(device_t dev)
468 {
469 struct msk_softc *sc;
470 struct msk_if_softc *sc_if;
471 struct mii_data *mii;
472 if_t ifp;
473 uint32_t gmac;
474
475 sc_if = device_get_softc(dev);
476 sc = sc_if->msk_softc;
477
478 MSK_IF_LOCK_ASSERT(sc_if);
479
480 mii = device_get_softc(sc_if->msk_miibus);
481 ifp = sc_if->msk_ifp;
482 if (mii == NULL || ifp == NULL ||
483 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
484 return;
485
486 sc_if->msk_flags &= ~MSK_FLAG_LINK;
487 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
488 (IFM_AVALID | IFM_ACTIVE)) {
489 switch (IFM_SUBTYPE(mii->mii_media_active)) {
490 case IFM_10_T:
491 case IFM_100_TX:
492 sc_if->msk_flags |= MSK_FLAG_LINK;
493 break;
494 case IFM_1000_T:
495 case IFM_1000_SX:
496 case IFM_1000_LX:
497 case IFM_1000_CX:
498 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
499 sc_if->msk_flags |= MSK_FLAG_LINK;
500 break;
501 default:
502 break;
503 }
504 }
505
506 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
507 /* Enable Tx FIFO Underrun. */
508 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
509 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
510 /*
511 * Because mii(4) notify msk(4) that it detected link status
512 * change, there is no need to enable automatic
513 * speed/flow-control/duplex updates.
514 */
515 gmac = GM_GPCR_AU_ALL_DIS;
516 switch (IFM_SUBTYPE(mii->mii_media_active)) {
517 case IFM_1000_SX:
518 case IFM_1000_T:
519 gmac |= GM_GPCR_SPEED_1000;
520 break;
521 case IFM_100_TX:
522 gmac |= GM_GPCR_SPEED_100;
523 break;
524 case IFM_10_T:
525 break;
526 }
527
528 if ((IFM_OPTIONS(mii->mii_media_active) &
529 IFM_ETH_RXPAUSE) == 0)
530 gmac |= GM_GPCR_FC_RX_DIS;
531 if ((IFM_OPTIONS(mii->mii_media_active) &
532 IFM_ETH_TXPAUSE) == 0)
533 gmac |= GM_GPCR_FC_TX_DIS;
534 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
535 gmac |= GM_GPCR_DUP_FULL;
536 else
537 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
538 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
539 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
540 /* Read again to ensure writing. */
541 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
542 gmac = GMC_PAUSE_OFF;
543 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
544 if ((IFM_OPTIONS(mii->mii_media_active) &
545 IFM_ETH_RXPAUSE) != 0)
546 gmac = GMC_PAUSE_ON;
547 }
548 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
549
550 /* Enable PHY interrupt for FIFO underrun/overflow. */
551 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
552 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
553 } else {
554 /*
555 * Link state changed to down.
556 * Disable PHY interrupts.
557 */
558 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
559 /* Disable Rx/Tx MAC. */
560 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
561 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
562 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
563 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
564 /* Read again to ensure writing. */
565 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
566 }
567 }
568 }
569
570 static u_int
msk_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)571 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
572 {
573 uint32_t *mchash = arg;
574 uint32_t crc;
575
576 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
577 /* Just want the 6 least significant bits. */
578 crc &= 0x3f;
579 /* Set the corresponding bit in the hash table. */
580 mchash[crc >> 5] |= 1 << (crc & 0x1f);
581
582 return (1);
583 }
584
585 static void
msk_rxfilter(struct msk_if_softc * sc_if)586 msk_rxfilter(struct msk_if_softc *sc_if)
587 {
588 struct msk_softc *sc;
589 if_t ifp;
590 uint32_t mchash[2];
591 uint16_t mode;
592
593 sc = sc_if->msk_softc;
594
595 MSK_IF_LOCK_ASSERT(sc_if);
596
597 ifp = sc_if->msk_ifp;
598
599 bzero(mchash, sizeof(mchash));
600 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
601 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
602 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
603 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
604 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
605 mchash[0] = 0xffff;
606 mchash[1] = 0xffff;
607 } else {
608 mode |= GM_RXCR_UCF_ENA;
609 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash);
610 if (mchash[0] != 0 || mchash[1] != 0)
611 mode |= GM_RXCR_MCF_ENA;
612 }
613
614 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
615 mchash[0] & 0xffff);
616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
617 (mchash[0] >> 16) & 0xffff);
618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
619 mchash[1] & 0xffff);
620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
621 (mchash[1] >> 16) & 0xffff);
622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
623 }
624
625 static void
msk_setvlan(struct msk_if_softc * sc_if,if_t ifp)626 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp)
627 {
628 struct msk_softc *sc;
629
630 sc = sc_if->msk_softc;
631 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
632 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
633 RX_VLAN_STRIP_ON);
634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
635 TX_VLAN_TAG_ON);
636 } else {
637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
638 RX_VLAN_STRIP_OFF);
639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
640 TX_VLAN_TAG_OFF);
641 }
642 }
643
644 static int
msk_rx_fill(struct msk_if_softc * sc_if,int jumbo)645 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
646 {
647 uint16_t idx;
648 int i;
649
650 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
651 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
652 /* Wait until controller executes OP_TCPSTART command. */
653 for (i = 100; i > 0; i--) {
654 DELAY(100);
655 idx = CSR_READ_2(sc_if->msk_softc,
656 Y2_PREF_Q_ADDR(sc_if->msk_rxq,
657 PREF_UNIT_GET_IDX_REG));
658 if (idx != 0)
659 break;
660 }
661 if (i == 0) {
662 device_printf(sc_if->msk_if_dev,
663 "prefetch unit stuck?\n");
664 return (ETIMEDOUT);
665 }
666 /*
667 * Fill consumed LE with free buffer. This can be done
668 * in Rx handler but we don't want to add special code
669 * in fast handler.
670 */
671 if (jumbo > 0) {
672 if (msk_jumbo_newbuf(sc_if, 0) != 0)
673 return (ENOBUFS);
674 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
675 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
676 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
677 } else {
678 if (msk_newbuf(sc_if, 0) != 0)
679 return (ENOBUFS);
680 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
681 sc_if->msk_cdata.msk_rx_ring_map,
682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
683 }
684 sc_if->msk_cdata.msk_rx_prod = 0;
685 CSR_WRITE_2(sc_if->msk_softc,
686 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
687 sc_if->msk_cdata.msk_rx_prod);
688 }
689 return (0);
690 }
691
692 static int
msk_init_rx_ring(struct msk_if_softc * sc_if)693 msk_init_rx_ring(struct msk_if_softc *sc_if)
694 {
695 struct msk_ring_data *rd;
696 struct msk_rxdesc *rxd;
697 int i, nbuf, prod;
698
699 MSK_IF_LOCK_ASSERT(sc_if);
700
701 sc_if->msk_cdata.msk_rx_cons = 0;
702 sc_if->msk_cdata.msk_rx_prod = 0;
703 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
704
705 rd = &sc_if->msk_rdata;
706 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
707 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
708 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
709 rxd->rx_m = NULL;
710 rxd->rx_le = &rd->msk_rx_ring[prod];
711 MSK_INC(prod, MSK_RX_RING_CNT);
712 }
713 nbuf = MSK_RX_BUF_CNT;
714 prod = 0;
715 /* Have controller know how to compute Rx checksum. */
716 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
717 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
718 #ifdef MSK_64BIT_DMA
719 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
720 rxd->rx_m = NULL;
721 rxd->rx_le = &rd->msk_rx_ring[prod];
722 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
723 ETHER_HDR_LEN);
724 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
725 MSK_INC(prod, MSK_RX_RING_CNT);
726 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
727 #endif
728 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
729 rxd->rx_m = NULL;
730 rxd->rx_le = &rd->msk_rx_ring[prod];
731 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
732 ETHER_HDR_LEN);
733 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
734 MSK_INC(prod, MSK_RX_RING_CNT);
735 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
736 nbuf--;
737 }
738 for (i = 0; i < nbuf; i++) {
739 if (msk_newbuf(sc_if, prod) != 0)
740 return (ENOBUFS);
741 MSK_RX_INC(prod, MSK_RX_RING_CNT);
742 }
743
744 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
745 sc_if->msk_cdata.msk_rx_ring_map,
746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
747
748 /* Update prefetch unit. */
749 sc_if->msk_cdata.msk_rx_prod = prod;
750 CSR_WRITE_2(sc_if->msk_softc,
751 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
752 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
753 MSK_RX_RING_CNT);
754 if (msk_rx_fill(sc_if, 0) != 0)
755 return (ENOBUFS);
756 return (0);
757 }
758
759 static int
msk_init_jumbo_rx_ring(struct msk_if_softc * sc_if)760 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
761 {
762 struct msk_ring_data *rd;
763 struct msk_rxdesc *rxd;
764 int i, nbuf, prod;
765
766 MSK_IF_LOCK_ASSERT(sc_if);
767
768 sc_if->msk_cdata.msk_rx_cons = 0;
769 sc_if->msk_cdata.msk_rx_prod = 0;
770 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
771
772 rd = &sc_if->msk_rdata;
773 bzero(rd->msk_jumbo_rx_ring,
774 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
775 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
776 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
777 rxd->rx_m = NULL;
778 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
779 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
780 }
781 nbuf = MSK_RX_BUF_CNT;
782 prod = 0;
783 /* Have controller know how to compute Rx checksum. */
784 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
785 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
786 #ifdef MSK_64BIT_DMA
787 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
788 rxd->rx_m = NULL;
789 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
790 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
791 ETHER_HDR_LEN);
792 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
793 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
794 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
795 #endif
796 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
797 rxd->rx_m = NULL;
798 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
799 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
800 ETHER_HDR_LEN);
801 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
802 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
803 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
804 nbuf--;
805 }
806 for (i = 0; i < nbuf; i++) {
807 if (msk_jumbo_newbuf(sc_if, prod) != 0)
808 return (ENOBUFS);
809 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT);
810 }
811
812 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
813 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
815
816 /* Update prefetch unit. */
817 sc_if->msk_cdata.msk_rx_prod = prod;
818 CSR_WRITE_2(sc_if->msk_softc,
819 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
820 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
821 MSK_JUMBO_RX_RING_CNT);
822 if (msk_rx_fill(sc_if, 1) != 0)
823 return (ENOBUFS);
824 return (0);
825 }
826
827 static void
msk_init_tx_ring(struct msk_if_softc * sc_if)828 msk_init_tx_ring(struct msk_if_softc *sc_if)
829 {
830 struct msk_ring_data *rd;
831 struct msk_txdesc *txd;
832 int i;
833
834 sc_if->msk_cdata.msk_tso_mtu = 0;
835 sc_if->msk_cdata.msk_last_csum = 0;
836 sc_if->msk_cdata.msk_tx_prod = 0;
837 sc_if->msk_cdata.msk_tx_cons = 0;
838 sc_if->msk_cdata.msk_tx_cnt = 0;
839 sc_if->msk_cdata.msk_tx_high_addr = 0;
840
841 rd = &sc_if->msk_rdata;
842 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
843 for (i = 0; i < MSK_TX_RING_CNT; i++) {
844 txd = &sc_if->msk_cdata.msk_txdesc[i];
845 txd->tx_m = NULL;
846 txd->tx_le = &rd->msk_tx_ring[i];
847 }
848
849 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
850 sc_if->msk_cdata.msk_tx_ring_map,
851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
852 }
853
854 static __inline void
msk_discard_rxbuf(struct msk_if_softc * sc_if,int idx)855 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
856 {
857 struct msk_rx_desc *rx_le;
858 struct msk_rxdesc *rxd;
859 struct mbuf *m;
860
861 #ifdef MSK_64BIT_DMA
862 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
863 rx_le = rxd->rx_le;
864 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
865 MSK_INC(idx, MSK_RX_RING_CNT);
866 #endif
867 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
868 m = rxd->rx_m;
869 rx_le = rxd->rx_le;
870 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
871 }
872
873 static __inline void
msk_discard_jumbo_rxbuf(struct msk_if_softc * sc_if,int idx)874 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
875 {
876 struct msk_rx_desc *rx_le;
877 struct msk_rxdesc *rxd;
878 struct mbuf *m;
879
880 #ifdef MSK_64BIT_DMA
881 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
882 rx_le = rxd->rx_le;
883 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
884 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
885 #endif
886 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
887 m = rxd->rx_m;
888 rx_le = rxd->rx_le;
889 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
890 }
891
892 static int
msk_newbuf(struct msk_if_softc * sc_if,int idx)893 msk_newbuf(struct msk_if_softc *sc_if, int idx)
894 {
895 struct msk_rx_desc *rx_le;
896 struct msk_rxdesc *rxd;
897 struct mbuf *m;
898 bus_dma_segment_t segs[1];
899 bus_dmamap_t map;
900 int nsegs;
901
902 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
903 if (m == NULL)
904 return (ENOBUFS);
905
906 m->m_len = m->m_pkthdr.len = MCLBYTES;
907 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
908 m_adj(m, ETHER_ALIGN);
909 #ifndef __NO_STRICT_ALIGNMENT
910 else
911 m_adj(m, MSK_RX_BUF_ALIGN);
912 #endif
913
914 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
915 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
916 BUS_DMA_NOWAIT) != 0) {
917 m_freem(m);
918 return (ENOBUFS);
919 }
920 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
921
922 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
923 #ifdef MSK_64BIT_DMA
924 rx_le = rxd->rx_le;
925 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
926 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
927 MSK_INC(idx, MSK_RX_RING_CNT);
928 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
929 #endif
930 if (rxd->rx_m != NULL) {
931 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
932 BUS_DMASYNC_POSTREAD);
933 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
934 rxd->rx_m = NULL;
935 }
936 map = rxd->rx_dmamap;
937 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
938 sc_if->msk_cdata.msk_rx_sparemap = map;
939 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
940 BUS_DMASYNC_PREREAD);
941 rxd->rx_m = m;
942 rx_le = rxd->rx_le;
943 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
944 rx_le->msk_control =
945 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
946
947 return (0);
948 }
949
950 static int
msk_jumbo_newbuf(struct msk_if_softc * sc_if,int idx)951 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
952 {
953 struct msk_rx_desc *rx_le;
954 struct msk_rxdesc *rxd;
955 struct mbuf *m;
956 bus_dma_segment_t segs[1];
957 bus_dmamap_t map;
958 int nsegs;
959
960 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
961 if (m == NULL)
962 return (ENOBUFS);
963 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
964 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
965 m_adj(m, ETHER_ALIGN);
966 #ifndef __NO_STRICT_ALIGNMENT
967 else
968 m_adj(m, MSK_RX_BUF_ALIGN);
969 #endif
970
971 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
972 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
973 BUS_DMA_NOWAIT) != 0) {
974 m_freem(m);
975 return (ENOBUFS);
976 }
977 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
978
979 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
980 #ifdef MSK_64BIT_DMA
981 rx_le = rxd->rx_le;
982 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
983 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
984 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
985 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
986 #endif
987 if (rxd->rx_m != NULL) {
988 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
989 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
990 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
991 rxd->rx_dmamap);
992 rxd->rx_m = NULL;
993 }
994 map = rxd->rx_dmamap;
995 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
996 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
997 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
998 BUS_DMASYNC_PREREAD);
999 rxd->rx_m = m;
1000 rx_le = rxd->rx_le;
1001 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1002 rx_le->msk_control =
1003 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
1004
1005 return (0);
1006 }
1007
1008 /*
1009 * Set media options.
1010 */
1011 static int
msk_mediachange(if_t ifp)1012 msk_mediachange(if_t ifp)
1013 {
1014 struct msk_if_softc *sc_if;
1015 struct mii_data *mii;
1016 int error;
1017
1018 sc_if = if_getsoftc(ifp);
1019
1020 MSK_IF_LOCK(sc_if);
1021 mii = device_get_softc(sc_if->msk_miibus);
1022 error = mii_mediachg(mii);
1023 MSK_IF_UNLOCK(sc_if);
1024
1025 return (error);
1026 }
1027
1028 /*
1029 * Report current media status.
1030 */
1031 static void
msk_mediastatus(if_t ifp,struct ifmediareq * ifmr)1032 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr)
1033 {
1034 struct msk_if_softc *sc_if;
1035 struct mii_data *mii;
1036
1037 sc_if = if_getsoftc(ifp);
1038 MSK_IF_LOCK(sc_if);
1039 if ((if_getflags(ifp) & IFF_UP) == 0) {
1040 MSK_IF_UNLOCK(sc_if);
1041 return;
1042 }
1043 mii = device_get_softc(sc_if->msk_miibus);
1044
1045 mii_pollstat(mii);
1046 ifmr->ifm_active = mii->mii_media_active;
1047 ifmr->ifm_status = mii->mii_media_status;
1048 MSK_IF_UNLOCK(sc_if);
1049 }
1050
1051 static int
msk_ioctl(if_t ifp,u_long command,caddr_t data)1052 msk_ioctl(if_t ifp, u_long command, caddr_t data)
1053 {
1054 struct msk_if_softc *sc_if;
1055 struct ifreq *ifr;
1056 struct mii_data *mii;
1057 int error, mask, reinit;
1058
1059 sc_if = if_getsoftc(ifp);
1060 ifr = (struct ifreq *)data;
1061 error = 0;
1062
1063 switch(command) {
1064 case SIOCSIFMTU:
1065 MSK_IF_LOCK(sc_if);
1066 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1067 error = EINVAL;
1068 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1069 if (ifr->ifr_mtu > ETHERMTU) {
1070 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1071 error = EINVAL;
1072 MSK_IF_UNLOCK(sc_if);
1073 break;
1074 }
1075 if ((sc_if->msk_flags &
1076 MSK_FLAG_JUMBO_NOCSUM) != 0) {
1077 if_sethwassistbits(ifp, 0,
1078 MSK_CSUM_FEATURES | CSUM_TSO);
1079 if_setcapenablebit(ifp, 0,
1080 IFCAP_TSO4 | IFCAP_TXCSUM);
1081 VLAN_CAPABILITIES(ifp);
1082 }
1083 }
1084 if_setmtu(ifp, ifr->ifr_mtu);
1085 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1086 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1087 msk_init_locked(sc_if);
1088 }
1089 }
1090 MSK_IF_UNLOCK(sc_if);
1091 break;
1092 case SIOCSIFFLAGS:
1093 MSK_IF_LOCK(sc_if);
1094 if ((if_getflags(ifp) & IFF_UP) != 0) {
1095 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
1096 ((if_getflags(ifp) ^ sc_if->msk_if_flags) &
1097 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1098 msk_rxfilter(sc_if);
1099 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1100 msk_init_locked(sc_if);
1101 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1102 msk_stop(sc_if);
1103 sc_if->msk_if_flags = if_getflags(ifp);
1104 MSK_IF_UNLOCK(sc_if);
1105 break;
1106 case SIOCADDMULTI:
1107 case SIOCDELMULTI:
1108 MSK_IF_LOCK(sc_if);
1109 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1110 msk_rxfilter(sc_if);
1111 MSK_IF_UNLOCK(sc_if);
1112 break;
1113 case SIOCGIFMEDIA:
1114 case SIOCSIFMEDIA:
1115 mii = device_get_softc(sc_if->msk_miibus);
1116 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1117 break;
1118 case SIOCSIFCAP:
1119 reinit = 0;
1120 MSK_IF_LOCK(sc_if);
1121 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1122 if ((mask & IFCAP_TXCSUM) != 0 &&
1123 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
1124 if_togglecapenable(ifp, IFCAP_TXCSUM);
1125 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0)
1126 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0);
1127 else
1128 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES);
1129 }
1130 if ((mask & IFCAP_RXCSUM) != 0 &&
1131 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) {
1132 if_togglecapenable(ifp, IFCAP_RXCSUM);
1133 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1134 reinit = 1;
1135 }
1136 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1137 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0)
1138 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
1139 if ((mask & IFCAP_TSO4) != 0 &&
1140 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) {
1141 if_togglecapenable(ifp, IFCAP_TSO4);
1142 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0)
1143 if_sethwassistbits(ifp, CSUM_TSO, 0);
1144 else
1145 if_sethwassistbits(ifp, 0, CSUM_TSO);
1146 }
1147 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1148 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0)
1149 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1150 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1151 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) {
1152 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1153 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0)
1154 if_setcapenablebit(ifp, 0,
1155 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1156 msk_setvlan(sc_if, ifp);
1157 }
1158 if (if_getmtu(ifp) > ETHERMTU &&
1159 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1160 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
1161 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
1162 }
1163 VLAN_CAPABILITIES(ifp);
1164 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1165 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1166 msk_init_locked(sc_if);
1167 }
1168 MSK_IF_UNLOCK(sc_if);
1169 break;
1170 default:
1171 error = ether_ioctl(ifp, command, data);
1172 break;
1173 }
1174
1175 return (error);
1176 }
1177
1178 static int
mskc_probe(device_t dev)1179 mskc_probe(device_t dev)
1180 {
1181 const struct msk_product *mp;
1182 uint16_t vendor, devid;
1183 int i;
1184
1185 vendor = pci_get_vendor(dev);
1186 devid = pci_get_device(dev);
1187 mp = msk_products;
1188 for (i = 0; i < nitems(msk_products); i++, mp++) {
1189 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1190 device_set_desc(dev, mp->msk_name);
1191 return (BUS_PROBE_DEFAULT);
1192 }
1193 }
1194
1195 return (ENXIO);
1196 }
1197
1198 static int
mskc_setup_rambuffer(struct msk_softc * sc)1199 mskc_setup_rambuffer(struct msk_softc *sc)
1200 {
1201 int next;
1202 int i;
1203
1204 /* Get adapter SRAM size. */
1205 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1206 if (bootverbose)
1207 device_printf(sc->msk_dev,
1208 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1209 if (sc->msk_ramsize == 0)
1210 return (0);
1211
1212 sc->msk_pflags |= MSK_FLAG_RAMBUF;
1213 /*
1214 * Give receiver 2/3 of memory and round down to the multiple
1215 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1216 * of 1024.
1217 */
1218 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1219 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1220 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1221 sc->msk_rxqstart[i] = next;
1222 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1223 next = sc->msk_rxqend[i] + 1;
1224 sc->msk_txqstart[i] = next;
1225 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1226 next = sc->msk_txqend[i] + 1;
1227 if (bootverbose) {
1228 device_printf(sc->msk_dev,
1229 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1230 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1231 sc->msk_rxqend[i]);
1232 device_printf(sc->msk_dev,
1233 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1234 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1235 sc->msk_txqend[i]);
1236 }
1237 }
1238
1239 return (0);
1240 }
1241
1242 static void
msk_phy_power(struct msk_softc * sc,int mode)1243 msk_phy_power(struct msk_softc *sc, int mode)
1244 {
1245 uint32_t our, val;
1246 int i;
1247
1248 switch (mode) {
1249 case MSK_PHY_POWERUP:
1250 /* Switch power to VCC (WA for VAUX problem). */
1251 CSR_WRITE_1(sc, B0_POWER_CTRL,
1252 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1253 /* Disable Core Clock Division, set Clock Select to 0. */
1254 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1255
1256 val = 0;
1257 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1258 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1259 /* Enable bits are inverted. */
1260 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1261 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1262 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1263 }
1264 /*
1265 * Enable PCI & Core Clock, enable clock gating for both Links.
1266 */
1267 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1268
1269 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1270 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1271 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1272 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1273 /* Deassert Low Power for 1st PHY. */
1274 our |= PCI_Y2_PHY1_COMA;
1275 if (sc->msk_num_port > 1)
1276 our |= PCI_Y2_PHY2_COMA;
1277 }
1278 }
1279 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1280 sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1281 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1282 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1283 val &= (PCI_FORCE_ASPM_REQUEST |
1284 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1285 PCI_ASPM_CLKRUN_REQUEST);
1286 /* Set all bits to 0 except bits 15..12. */
1287 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1288 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1289 val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1290 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1291 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1292 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1293 /*
1294 * Disable status race, workaround for
1295 * Yukon EC Ultra & Yukon EX.
1296 */
1297 val = CSR_READ_4(sc, B2_GP_IO);
1298 val |= GLB_GPIO_STAT_RACE_DIS;
1299 CSR_WRITE_4(sc, B2_GP_IO, val);
1300 CSR_READ_4(sc, B2_GP_IO);
1301 }
1302 /* Release PHY from PowerDown/COMA mode. */
1303 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1304
1305 for (i = 0; i < sc->msk_num_port; i++) {
1306 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1307 GMLC_RST_SET);
1308 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1309 GMLC_RST_CLR);
1310 }
1311 break;
1312 case MSK_PHY_POWERDOWN:
1313 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1314 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1315 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1316 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1317 val &= ~PCI_Y2_PHY1_COMA;
1318 if (sc->msk_num_port > 1)
1319 val &= ~PCI_Y2_PHY2_COMA;
1320 }
1321 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1322
1323 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1324 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1325 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1326 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1327 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1328 /* Enable bits are inverted. */
1329 val = 0;
1330 }
1331 /*
1332 * Disable PCI & Core Clock, disable clock gating for
1333 * both Links.
1334 */
1335 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1336 CSR_WRITE_1(sc, B0_POWER_CTRL,
1337 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1338 break;
1339 default:
1340 break;
1341 }
1342 }
1343
1344 static void
mskc_reset(struct msk_softc * sc)1345 mskc_reset(struct msk_softc *sc)
1346 {
1347 bus_addr_t addr;
1348 uint16_t status;
1349 uint32_t val;
1350 int i, initram;
1351
1352 /* Disable ASF. */
1353 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1354 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1355 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1356 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1357 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1358 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1359 /* Clear AHB bridge & microcontroller reset. */
1360 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1361 Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1362 /* Clear ASF microcontroller state. */
1363 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1364 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
1365 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1366 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1367 } else
1368 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1369 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1370 /*
1371 * Since we disabled ASF, S/W reset is required for
1372 * Power Management.
1373 */
1374 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1376 }
1377
1378 /* Clear all error bits in the PCI status register. */
1379 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1380 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1381
1382 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1383 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1384 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
1385 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1386
1387 switch (sc->msk_bustype) {
1388 case MSK_PEX_BUS:
1389 /* Clear all PEX errors. */
1390 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1391 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1392 if ((val & PEX_RX_OV) != 0) {
1393 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1394 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1395 }
1396 break;
1397 case MSK_PCI_BUS:
1398 case MSK_PCIX_BUS:
1399 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1400 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1401 if (val == 0)
1402 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1403 if (sc->msk_bustype == MSK_PCIX_BUS) {
1404 /* Set Cache Line Size opt. */
1405 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1406 val |= PCI_CLS_OPT;
1407 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1408 }
1409 break;
1410 }
1411 /* Set PHY power state. */
1412 msk_phy_power(sc, MSK_PHY_POWERUP);
1413
1414 /* Reset GPHY/GMAC Control */
1415 for (i = 0; i < sc->msk_num_port; i++) {
1416 /* GPHY Control reset. */
1417 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1419 /* GMAC Control reset. */
1420 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1423 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1424 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1425 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1426 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1427 GMC_BYP_RETR_ON);
1428 }
1429
1430 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1431 sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1432 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS);
1433 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1434 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1435 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1436 }
1437 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1438
1439 /* LED On. */
1440 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1441
1442 /* Clear TWSI IRQ. */
1443 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1444
1445 /* Turn off hardware timer. */
1446 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1447 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1448
1449 /* Turn off descriptor polling. */
1450 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1451
1452 /* Turn off time stamps. */
1453 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1454 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1455
1456 initram = 0;
1457 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1458 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1459 sc->msk_hw_id == CHIP_ID_YUKON_FE)
1460 initram++;
1461
1462 /* Configure timeout values. */
1463 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1464 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1465 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1466 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1467 MSK_RI_TO_53);
1468 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1469 MSK_RI_TO_53);
1470 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1471 MSK_RI_TO_53);
1472 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1473 MSK_RI_TO_53);
1474 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1475 MSK_RI_TO_53);
1476 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1477 MSK_RI_TO_53);
1478 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1479 MSK_RI_TO_53);
1480 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1481 MSK_RI_TO_53);
1482 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1483 MSK_RI_TO_53);
1484 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1485 MSK_RI_TO_53);
1486 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1487 MSK_RI_TO_53);
1488 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1489 MSK_RI_TO_53);
1490 }
1491
1492 /* Disable all interrupts. */
1493 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1494 CSR_READ_4(sc, B0_HWE_IMSK);
1495 CSR_WRITE_4(sc, B0_IMSK, 0);
1496 CSR_READ_4(sc, B0_IMSK);
1497
1498 /*
1499 * On dual port PCI-X card, there is an problem where status
1500 * can be received out of order due to split transactions.
1501 */
1502 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1503 uint16_t pcix_cmd;
1504
1505 pcix_cmd = pci_read_config(sc->msk_dev,
1506 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1507 /* Clear Max Outstanding Split Transactions. */
1508 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1510 pci_write_config(sc->msk_dev,
1511 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1512 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1513 }
1514 if (sc->msk_expcap != 0) {
1515 /* Change Max. Read Request Size to 2048 bytes. */
1516 if (pci_get_max_read_req(sc->msk_dev) == 512)
1517 pci_set_max_read_req(sc->msk_dev, 2048);
1518 }
1519
1520 /* Clear status list. */
1521 bzero(sc->msk_stat_ring,
1522 sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1523 sc->msk_stat_cons = 0;
1524 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1526 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1528 /* Set the status list base address. */
1529 addr = sc->msk_stat_ring_paddr;
1530 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1532 /* Set the status list last index. */
1533 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1534 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1535 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1536 /* WA for dev. #4.3 */
1537 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1538 /* WA for dev. #4.18 */
1539 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1540 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1541 } else {
1542 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1543 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1544 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1545 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1546 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1547 else
1548 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1549 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1550 }
1551 /*
1552 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1553 */
1554 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1555
1556 /* Enable status unit. */
1557 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1558
1559 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1560 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1561 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1562 }
1563
1564 static int
msk_probe(device_t dev)1565 msk_probe(device_t dev)
1566 {
1567 struct msk_softc *sc;
1568
1569 sc = device_get_softc(device_get_parent(dev));
1570 /*
1571 * Not much to do here. We always know there will be
1572 * at least one GMAC present, and if there are two,
1573 * mskc_attach() will create a second device instance
1574 * for us.
1575 */
1576 device_set_descf(dev,
1577 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1578 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1579 sc->msk_hw_rev);
1580
1581 return (BUS_PROBE_DEFAULT);
1582 }
1583
1584 static int
msk_attach(device_t dev)1585 msk_attach(device_t dev)
1586 {
1587 struct msk_softc *sc;
1588 struct msk_if_softc *sc_if;
1589 if_t ifp;
1590 struct msk_mii_data *mmd;
1591 int i, port, error;
1592 uint8_t eaddr[6];
1593
1594 if (dev == NULL)
1595 return (EINVAL);
1596
1597 error = 0;
1598 sc_if = device_get_softc(dev);
1599 sc = device_get_softc(device_get_parent(dev));
1600 mmd = device_get_ivars(dev);
1601 port = mmd->port;
1602
1603 sc_if->msk_if_dev = dev;
1604 sc_if->msk_port = port;
1605 sc_if->msk_softc = sc;
1606 sc_if->msk_flags = sc->msk_pflags;
1607 sc->msk_if[port] = sc_if;
1608 /* Setup Tx/Rx queue register offsets. */
1609 if (port == MSK_PORT_A) {
1610 sc_if->msk_txq = Q_XA1;
1611 sc_if->msk_txsq = Q_XS1;
1612 sc_if->msk_rxq = Q_R1;
1613 } else {
1614 sc_if->msk_txq = Q_XA2;
1615 sc_if->msk_txsq = Q_XS2;
1616 sc_if->msk_rxq = Q_R2;
1617 }
1618
1619 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1620 msk_sysctl_node(sc_if);
1621
1622 if ((error = msk_txrx_dma_alloc(sc_if)) != 0)
1623 goto fail;
1624 msk_rx_dma_jalloc(sc_if);
1625
1626 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1627 if_setsoftc(ifp, sc_if);
1628 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1629 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1630 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4);
1631 /*
1632 * Enable Rx checksum offloading if controller supports
1633 * new descriptor formant and controller is not Yukon XL.
1634 */
1635 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1636 sc->msk_hw_id != CHIP_ID_YUKON_XL)
1637 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1638 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1639 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1640 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1641 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO);
1642 if_setcapenable(ifp, if_getcapabilities(ifp));
1643 if_setioctlfn(ifp, msk_ioctl);
1644 if_setstartfn(ifp, msk_start);
1645 if_setinitfn(ifp, msk_init);
1646 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1);
1647 if_setsendqready(ifp);
1648 /*
1649 * Get station address for this interface. Note that
1650 * dual port cards actually come with three station
1651 * addresses: one for each port, plus an extra. The
1652 * extra one is used by the SysKonnect driver software
1653 * as a 'virtual' station address for when both ports
1654 * are operating in failover mode. Currently we don't
1655 * use this extra address.
1656 */
1657 MSK_IF_LOCK(sc_if);
1658 for (i = 0; i < ETHER_ADDR_LEN; i++)
1659 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1660
1661 /*
1662 * Call MI attach routine. Can't hold locks when calling into ether_*.
1663 */
1664 MSK_IF_UNLOCK(sc_if);
1665 ether_ifattach(ifp, eaddr);
1666 MSK_IF_LOCK(sc_if);
1667
1668 /* VLAN capability setup */
1669 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1670 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1671 /*
1672 * Due to Tx checksum offload hardware bugs, msk(4) manually
1673 * computes checksum for short frames. For VLAN tagged frames
1674 * this workaround does not work so disable checksum offload
1675 * for VLAN interface.
1676 */
1677 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0);
1678 /*
1679 * Enable Rx checksum offloading for VLAN tagged frames
1680 * if controller support new descriptor format.
1681 */
1682 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1683 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1684 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
1685 }
1686 if_setcapenable(ifp, if_getcapabilities(ifp));
1687 /*
1688 * Disable RX checksum offloading on controllers that don't use
1689 * new descriptor format but give chance to enable it.
1690 */
1691 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1692 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
1693
1694 /*
1695 * Tell the upper layer(s) we support long frames.
1696 * Must appear after the call to ether_ifattach() because
1697 * ether_ifattach() sets ifi_hdrlen to the default value.
1698 */
1699 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1700
1701 /*
1702 * Do miibus setup.
1703 */
1704 MSK_IF_UNLOCK(sc_if);
1705 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1706 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
1707 mmd->mii_flags);
1708 if (error != 0) {
1709 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1710 ether_ifdetach(ifp);
1711 error = ENXIO;
1712 goto fail;
1713 }
1714
1715 fail:
1716 if (error != 0) {
1717 /* Access should be ok even though lock has been dropped */
1718 sc->msk_if[port] = NULL;
1719 msk_detach(dev);
1720 }
1721
1722 return (error);
1723 }
1724
1725 /*
1726 * Attach the interface. Allocate softc structures, do ifmedia
1727 * setup and ethernet/BPF attach.
1728 */
1729 static int
mskc_attach(device_t dev)1730 mskc_attach(device_t dev)
1731 {
1732 struct msk_softc *sc;
1733 struct msk_mii_data *mmd;
1734 int error, msic, msir, reg;
1735
1736 sc = device_get_softc(dev);
1737 sc->msk_dev = dev;
1738 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1739 MTX_DEF);
1740
1741 /*
1742 * Map control/status registers.
1743 */
1744 pci_enable_busmaster(dev);
1745
1746 /* Allocate I/O resource */
1747 #ifdef MSK_USEIOSPACE
1748 sc->msk_res_spec = msk_res_spec_io;
1749 #else
1750 sc->msk_res_spec = msk_res_spec_mem;
1751 #endif
1752 sc->msk_irq_spec = msk_irq_spec_legacy;
1753 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1754 if (error) {
1755 if (sc->msk_res_spec == msk_res_spec_mem)
1756 sc->msk_res_spec = msk_res_spec_io;
1757 else
1758 sc->msk_res_spec = msk_res_spec_mem;
1759 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1760 if (error) {
1761 device_printf(dev, "couldn't allocate %s resources\n",
1762 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1763 "I/O");
1764 mtx_destroy(&sc->msk_mtx);
1765 return (ENXIO);
1766 }
1767 }
1768
1769 /* Enable all clocks before accessing any registers. */
1770 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1771
1772 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1773 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1774 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1775 /* Bail out if chip is not recognized. */
1776 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1777 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1778 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1779 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1780 sc->msk_hw_id, sc->msk_hw_rev);
1781 mtx_destroy(&sc->msk_mtx);
1782 return (ENXIO);
1783 }
1784
1785 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1786 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1787 OID_AUTO, "process_limit",
1788 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1789 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1790 "max number of Rx events to process");
1791
1792 sc->msk_process_limit = MSK_PROC_DEFAULT;
1793 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1794 "process_limit", &sc->msk_process_limit);
1795 if (error == 0) {
1796 if (sc->msk_process_limit < MSK_PROC_MIN ||
1797 sc->msk_process_limit > MSK_PROC_MAX) {
1798 device_printf(dev, "process_limit value out of range; "
1799 "using default: %d\n", MSK_PROC_DEFAULT);
1800 sc->msk_process_limit = MSK_PROC_DEFAULT;
1801 }
1802 }
1803
1804 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1805 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1807 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1808 "Maximum number of time to delay interrupts");
1809 resource_int_value(device_get_name(dev), device_get_unit(dev),
1810 "int_holdoff", &sc->msk_int_holdoff);
1811
1812 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1813 /* Check number of MACs. */
1814 sc->msk_num_port = 1;
1815 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1816 CFG_DUAL_MAC_MSK) {
1817 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1818 sc->msk_num_port++;
1819 }
1820
1821 /* Check bus type. */
1822 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
1823 sc->msk_bustype = MSK_PEX_BUS;
1824 sc->msk_expcap = reg;
1825 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
1826 sc->msk_bustype = MSK_PCIX_BUS;
1827 sc->msk_pcixcap = reg;
1828 } else
1829 sc->msk_bustype = MSK_PCI_BUS;
1830
1831 switch (sc->msk_hw_id) {
1832 case CHIP_ID_YUKON_EC:
1833 sc->msk_clock = 125; /* 125 MHz */
1834 sc->msk_pflags |= MSK_FLAG_JUMBO;
1835 break;
1836 case CHIP_ID_YUKON_EC_U:
1837 sc->msk_clock = 125; /* 125 MHz */
1838 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1839 break;
1840 case CHIP_ID_YUKON_EX:
1841 sc->msk_clock = 125; /* 125 MHz */
1842 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1843 MSK_FLAG_AUTOTX_CSUM;
1844 /*
1845 * Yukon Extreme seems to have silicon bug for
1846 * automatic Tx checksum calculation capability.
1847 */
1848 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1849 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1850 /*
1851 * Yukon Extreme A0 could not use store-and-forward
1852 * for jumbo frames, so disable Tx checksum
1853 * offloading for jumbo frames.
1854 */
1855 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1856 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1857 break;
1858 case CHIP_ID_YUKON_FE:
1859 sc->msk_clock = 100; /* 100 MHz */
1860 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1861 break;
1862 case CHIP_ID_YUKON_FE_P:
1863 sc->msk_clock = 50; /* 50 MHz */
1864 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1865 MSK_FLAG_AUTOTX_CSUM;
1866 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1867 /*
1868 * XXX
1869 * FE+ A0 has status LE writeback bug so msk(4)
1870 * does not rely on status word of received frame
1871 * in msk_rxeof() which in turn disables all
1872 * hardware assistance bits reported by the status
1873 * word as well as validity of the received frame.
1874 * Just pass received frames to upper stack with
1875 * minimal test and let upper stack handle them.
1876 */
1877 sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1878 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1879 }
1880 break;
1881 case CHIP_ID_YUKON_XL:
1882 sc->msk_clock = 156; /* 156 MHz */
1883 sc->msk_pflags |= MSK_FLAG_JUMBO;
1884 break;
1885 case CHIP_ID_YUKON_SUPR:
1886 sc->msk_clock = 125; /* 125 MHz */
1887 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1888 MSK_FLAG_AUTOTX_CSUM;
1889 break;
1890 case CHIP_ID_YUKON_UL_2:
1891 sc->msk_clock = 125; /* 125 MHz */
1892 sc->msk_pflags |= MSK_FLAG_JUMBO;
1893 break;
1894 case CHIP_ID_YUKON_OPT:
1895 sc->msk_clock = 125; /* 125 MHz */
1896 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1897 break;
1898 default:
1899 sc->msk_clock = 156; /* 156 MHz */
1900 break;
1901 }
1902
1903 /* Allocate IRQ resources. */
1904 msic = pci_msi_count(dev);
1905 if (bootverbose)
1906 device_printf(dev, "MSI count : %d\n", msic);
1907 if (legacy_intr != 0)
1908 msi_disable = 1;
1909 if (msi_disable == 0 && msic > 0) {
1910 msir = 1;
1911 if (pci_alloc_msi(dev, &msir) == 0) {
1912 if (msir == 1) {
1913 sc->msk_pflags |= MSK_FLAG_MSI;
1914 sc->msk_irq_spec = msk_irq_spec_msi;
1915 } else
1916 pci_release_msi(dev);
1917 }
1918 }
1919
1920 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1921 if (error) {
1922 device_printf(dev, "couldn't allocate IRQ resources\n");
1923 goto fail;
1924 }
1925
1926 if ((error = msk_status_dma_alloc(sc)) != 0)
1927 goto fail;
1928
1929 /* Set base interrupt mask. */
1930 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1931 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1932 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1933
1934 /* Reset the adapter. */
1935 mskc_reset(sc);
1936
1937 if ((error = mskc_setup_rambuffer(sc)) != 0)
1938 goto fail;
1939
1940 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1941 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1942 device_printf(dev, "failed to add child for PORT_A\n");
1943 error = ENXIO;
1944 goto fail;
1945 }
1946 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1947 mmd->port = MSK_PORT_A;
1948 mmd->pmd = sc->msk_pmd;
1949 mmd->mii_flags |= MIIF_DOPAUSE;
1950 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1951 mmd->mii_flags |= MIIF_HAVEFIBER;
1952 if (sc->msk_pmd == 'P')
1953 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1954 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1955
1956 if (sc->msk_num_port > 1) {
1957 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1958 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1959 device_printf(dev, "failed to add child for PORT_B\n");
1960 error = ENXIO;
1961 goto fail;
1962 }
1963 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
1964 M_ZERO);
1965 mmd->port = MSK_PORT_B;
1966 mmd->pmd = sc->msk_pmd;
1967 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1968 mmd->mii_flags |= MIIF_HAVEFIBER;
1969 if (sc->msk_pmd == 'P')
1970 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1971 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1972 }
1973
1974 error = bus_generic_attach(dev);
1975 if (error) {
1976 device_printf(dev, "failed to attach port(s)\n");
1977 goto fail;
1978 }
1979
1980 /* Hook interrupt last to avoid having to lock softc. */
1981 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1982 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
1983 if (error != 0) {
1984 device_printf(dev, "couldn't set up interrupt handler\n");
1985 goto fail;
1986 }
1987 fail:
1988 if (error != 0)
1989 mskc_detach(dev);
1990
1991 return (error);
1992 }
1993
1994 /*
1995 * Shutdown hardware and free up resources. This can be called any
1996 * time after the mutex has been initialized. It is called in both
1997 * the error case in attach and the normal detach case so it needs
1998 * to be careful about only freeing resources that have actually been
1999 * allocated.
2000 */
2001 static int
msk_detach(device_t dev)2002 msk_detach(device_t dev)
2003 {
2004 struct msk_softc *sc;
2005 struct msk_if_softc *sc_if;
2006 if_t ifp;
2007
2008 sc_if = device_get_softc(dev);
2009 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2010 ("msk mutex not initialized in msk_detach"));
2011 MSK_IF_LOCK(sc_if);
2012
2013 ifp = sc_if->msk_ifp;
2014 if (device_is_attached(dev)) {
2015 /* XXX */
2016 sc_if->msk_flags |= MSK_FLAG_DETACH;
2017 msk_stop(sc_if);
2018 /* Can't hold locks while calling detach. */
2019 MSK_IF_UNLOCK(sc_if);
2020 callout_drain(&sc_if->msk_tick_ch);
2021 if (ifp)
2022 ether_ifdetach(ifp);
2023 MSK_IF_LOCK(sc_if);
2024 }
2025
2026 /*
2027 * We're generally called from mskc_detach() which is using
2028 * device_delete_child() to get to here. It's already trashed
2029 * miibus for us, so don't do it here or we'll panic.
2030 *
2031 * if (sc_if->msk_miibus != NULL) {
2032 * device_delete_child(dev, sc_if->msk_miibus);
2033 * sc_if->msk_miibus = NULL;
2034 * }
2035 */
2036
2037 msk_rx_dma_jfree(sc_if);
2038 msk_txrx_dma_free(sc_if);
2039 bus_generic_detach(dev);
2040
2041 sc = sc_if->msk_softc;
2042 sc->msk_if[sc_if->msk_port] = NULL;
2043 MSK_IF_UNLOCK(sc_if);
2044 if (ifp)
2045 if_free(ifp);
2046
2047 return (0);
2048 }
2049
2050 static int
mskc_detach(device_t dev)2051 mskc_detach(device_t dev)
2052 {
2053 struct msk_softc *sc;
2054
2055 sc = device_get_softc(dev);
2056 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2057
2058 if (device_is_alive(dev)) {
2059 if (sc->msk_devs[MSK_PORT_A] != NULL) {
2060 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
2061 M_DEVBUF);
2062 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
2063 }
2064 if (sc->msk_devs[MSK_PORT_B] != NULL) {
2065 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
2066 M_DEVBUF);
2067 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
2068 }
2069 bus_generic_detach(dev);
2070 }
2071
2072 /* Disable all interrupts. */
2073 CSR_WRITE_4(sc, B0_IMSK, 0);
2074 CSR_READ_4(sc, B0_IMSK);
2075 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2076 CSR_READ_4(sc, B0_HWE_IMSK);
2077
2078 /* LED Off. */
2079 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
2080
2081 /* Put hardware reset. */
2082 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2083
2084 msk_status_dma_free(sc);
2085
2086 if (sc->msk_intrhand) {
2087 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2088 sc->msk_intrhand = NULL;
2089 }
2090 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2091 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2092 pci_release_msi(dev);
2093 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2094 mtx_destroy(&sc->msk_mtx);
2095
2096 return (0);
2097 }
2098
2099 static bus_dma_tag_t
mskc_get_dma_tag(device_t bus,device_t child __unused)2100 mskc_get_dma_tag(device_t bus, device_t child __unused)
2101 {
2102
2103 return (bus_get_dma_tag(bus));
2104 }
2105
2106 struct msk_dmamap_arg {
2107 bus_addr_t msk_busaddr;
2108 };
2109
2110 static void
msk_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)2111 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2112 {
2113 struct msk_dmamap_arg *ctx;
2114
2115 if (error != 0)
2116 return;
2117 ctx = arg;
2118 ctx->msk_busaddr = segs[0].ds_addr;
2119 }
2120
2121 /* Create status DMA region. */
2122 static int
msk_status_dma_alloc(struct msk_softc * sc)2123 msk_status_dma_alloc(struct msk_softc *sc)
2124 {
2125 struct msk_dmamap_arg ctx;
2126 bus_size_t stat_sz;
2127 int count, error;
2128
2129 /*
2130 * It seems controller requires number of status LE entries
2131 * is power of 2 and the maximum number of status LE entries
2132 * is 4096. For dual-port controllers, the number of status
2133 * LE entries should be large enough to hold both port's
2134 * status updates.
2135 */
2136 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT;
2137 count = imin(4096, roundup2(count, 1024));
2138 sc->msk_stat_count = count;
2139 stat_sz = count * sizeof(struct msk_stat_desc);
2140 error = bus_dma_tag_create(
2141 bus_get_dma_tag(sc->msk_dev), /* parent */
2142 MSK_STAT_ALIGN, 0, /* alignment, boundary */
2143 BUS_SPACE_MAXADDR, /* lowaddr */
2144 BUS_SPACE_MAXADDR, /* highaddr */
2145 NULL, NULL, /* filter, filterarg */
2146 stat_sz, /* maxsize */
2147 1, /* nsegments */
2148 stat_sz, /* maxsegsize */
2149 0, /* flags */
2150 NULL, NULL, /* lockfunc, lockarg */
2151 &sc->msk_stat_tag);
2152 if (error != 0) {
2153 device_printf(sc->msk_dev,
2154 "failed to create status DMA tag\n");
2155 return (error);
2156 }
2157
2158 /* Allocate DMA'able memory and load the DMA map for status ring. */
2159 error = bus_dmamem_alloc(sc->msk_stat_tag,
2160 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2161 BUS_DMA_ZERO, &sc->msk_stat_map);
2162 if (error != 0) {
2163 device_printf(sc->msk_dev,
2164 "failed to allocate DMA'able memory for status ring\n");
2165 return (error);
2166 }
2167
2168 ctx.msk_busaddr = 0;
2169 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2170 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2171 if (error != 0) {
2172 device_printf(sc->msk_dev,
2173 "failed to load DMA'able memory for status ring\n");
2174 return (error);
2175 }
2176 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2177
2178 return (0);
2179 }
2180
2181 static void
msk_status_dma_free(struct msk_softc * sc)2182 msk_status_dma_free(struct msk_softc *sc)
2183 {
2184
2185 /* Destroy status block. */
2186 if (sc->msk_stat_tag) {
2187 if (sc->msk_stat_ring_paddr) {
2188 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2189 sc->msk_stat_ring_paddr = 0;
2190 }
2191 if (sc->msk_stat_ring) {
2192 bus_dmamem_free(sc->msk_stat_tag,
2193 sc->msk_stat_ring, sc->msk_stat_map);
2194 sc->msk_stat_ring = NULL;
2195 }
2196 bus_dma_tag_destroy(sc->msk_stat_tag);
2197 sc->msk_stat_tag = NULL;
2198 }
2199 }
2200
2201 static int
msk_txrx_dma_alloc(struct msk_if_softc * sc_if)2202 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2203 {
2204 struct msk_dmamap_arg ctx;
2205 struct msk_txdesc *txd;
2206 struct msk_rxdesc *rxd;
2207 bus_size_t rxalign;
2208 int error, i;
2209
2210 /* Create parent DMA tag. */
2211 error = bus_dma_tag_create(
2212 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2213 1, 0, /* alignment, boundary */
2214 BUS_SPACE_MAXADDR, /* lowaddr */
2215 BUS_SPACE_MAXADDR, /* highaddr */
2216 NULL, NULL, /* filter, filterarg */
2217 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2218 0, /* nsegments */
2219 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2220 0, /* flags */
2221 NULL, NULL, /* lockfunc, lockarg */
2222 &sc_if->msk_cdata.msk_parent_tag);
2223 if (error != 0) {
2224 device_printf(sc_if->msk_if_dev,
2225 "failed to create parent DMA tag\n");
2226 goto fail;
2227 }
2228 /* Create tag for Tx ring. */
2229 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2230 MSK_RING_ALIGN, 0, /* alignment, boundary */
2231 BUS_SPACE_MAXADDR, /* lowaddr */
2232 BUS_SPACE_MAXADDR, /* highaddr */
2233 NULL, NULL, /* filter, filterarg */
2234 MSK_TX_RING_SZ, /* maxsize */
2235 1, /* nsegments */
2236 MSK_TX_RING_SZ, /* maxsegsize */
2237 0, /* flags */
2238 NULL, NULL, /* lockfunc, lockarg */
2239 &sc_if->msk_cdata.msk_tx_ring_tag);
2240 if (error != 0) {
2241 device_printf(sc_if->msk_if_dev,
2242 "failed to create Tx ring DMA tag\n");
2243 goto fail;
2244 }
2245
2246 /* Create tag for Rx ring. */
2247 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2248 MSK_RING_ALIGN, 0, /* alignment, boundary */
2249 BUS_SPACE_MAXADDR, /* lowaddr */
2250 BUS_SPACE_MAXADDR, /* highaddr */
2251 NULL, NULL, /* filter, filterarg */
2252 MSK_RX_RING_SZ, /* maxsize */
2253 1, /* nsegments */
2254 MSK_RX_RING_SZ, /* maxsegsize */
2255 0, /* flags */
2256 NULL, NULL, /* lockfunc, lockarg */
2257 &sc_if->msk_cdata.msk_rx_ring_tag);
2258 if (error != 0) {
2259 device_printf(sc_if->msk_if_dev,
2260 "failed to create Rx ring DMA tag\n");
2261 goto fail;
2262 }
2263
2264 /* Create tag for Tx buffers. */
2265 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2266 1, 0, /* alignment, boundary */
2267 BUS_SPACE_MAXADDR, /* lowaddr */
2268 BUS_SPACE_MAXADDR, /* highaddr */
2269 NULL, NULL, /* filter, filterarg */
2270 MSK_TSO_MAXSIZE, /* maxsize */
2271 MSK_MAXTXSEGS, /* nsegments */
2272 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2273 0, /* flags */
2274 NULL, NULL, /* lockfunc, lockarg */
2275 &sc_if->msk_cdata.msk_tx_tag);
2276 if (error != 0) {
2277 device_printf(sc_if->msk_if_dev,
2278 "failed to create Tx DMA tag\n");
2279 goto fail;
2280 }
2281
2282 rxalign = 1;
2283 /*
2284 * Workaround hardware hang which seems to happen when Rx buffer
2285 * is not aligned on multiple of FIFO word(8 bytes).
2286 */
2287 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2288 rxalign = MSK_RX_BUF_ALIGN;
2289 /* Create tag for Rx buffers. */
2290 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2291 rxalign, 0, /* alignment, boundary */
2292 BUS_SPACE_MAXADDR, /* lowaddr */
2293 BUS_SPACE_MAXADDR, /* highaddr */
2294 NULL, NULL, /* filter, filterarg */
2295 MCLBYTES, /* maxsize */
2296 1, /* nsegments */
2297 MCLBYTES, /* maxsegsize */
2298 0, /* flags */
2299 NULL, NULL, /* lockfunc, lockarg */
2300 &sc_if->msk_cdata.msk_rx_tag);
2301 if (error != 0) {
2302 device_printf(sc_if->msk_if_dev,
2303 "failed to create Rx DMA tag\n");
2304 goto fail;
2305 }
2306
2307 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2308 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2309 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2310 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2311 if (error != 0) {
2312 device_printf(sc_if->msk_if_dev,
2313 "failed to allocate DMA'able memory for Tx ring\n");
2314 goto fail;
2315 }
2316
2317 ctx.msk_busaddr = 0;
2318 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2319 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2320 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2321 if (error != 0) {
2322 device_printf(sc_if->msk_if_dev,
2323 "failed to load DMA'able memory for Tx ring\n");
2324 goto fail;
2325 }
2326 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2327
2328 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2329 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2330 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2331 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2332 if (error != 0) {
2333 device_printf(sc_if->msk_if_dev,
2334 "failed to allocate DMA'able memory for Rx ring\n");
2335 goto fail;
2336 }
2337
2338 ctx.msk_busaddr = 0;
2339 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2340 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2341 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2342 if (error != 0) {
2343 device_printf(sc_if->msk_if_dev,
2344 "failed to load DMA'able memory for Rx ring\n");
2345 goto fail;
2346 }
2347 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2348
2349 /* Create DMA maps for Tx buffers. */
2350 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2351 txd = &sc_if->msk_cdata.msk_txdesc[i];
2352 txd->tx_m = NULL;
2353 txd->tx_dmamap = NULL;
2354 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2355 &txd->tx_dmamap);
2356 if (error != 0) {
2357 device_printf(sc_if->msk_if_dev,
2358 "failed to create Tx dmamap\n");
2359 goto fail;
2360 }
2361 }
2362 /* Create DMA maps for Rx buffers. */
2363 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2364 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2365 device_printf(sc_if->msk_if_dev,
2366 "failed to create spare Rx dmamap\n");
2367 goto fail;
2368 }
2369 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2370 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2371 rxd->rx_m = NULL;
2372 rxd->rx_dmamap = NULL;
2373 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2374 &rxd->rx_dmamap);
2375 if (error != 0) {
2376 device_printf(sc_if->msk_if_dev,
2377 "failed to create Rx dmamap\n");
2378 goto fail;
2379 }
2380 }
2381
2382 fail:
2383 return (error);
2384 }
2385
2386 static int
msk_rx_dma_jalloc(struct msk_if_softc * sc_if)2387 msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
2388 {
2389 struct msk_dmamap_arg ctx;
2390 struct msk_rxdesc *jrxd;
2391 bus_size_t rxalign;
2392 int error, i;
2393
2394 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2395 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2396 device_printf(sc_if->msk_if_dev,
2397 "disabling jumbo frame support\n");
2398 return (0);
2399 }
2400 /* Create tag for jumbo Rx ring. */
2401 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2402 MSK_RING_ALIGN, 0, /* alignment, boundary */
2403 BUS_SPACE_MAXADDR, /* lowaddr */
2404 BUS_SPACE_MAXADDR, /* highaddr */
2405 NULL, NULL, /* filter, filterarg */
2406 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2407 1, /* nsegments */
2408 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2409 0, /* flags */
2410 NULL, NULL, /* lockfunc, lockarg */
2411 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2412 if (error != 0) {
2413 device_printf(sc_if->msk_if_dev,
2414 "failed to create jumbo Rx ring DMA tag\n");
2415 goto jumbo_fail;
2416 }
2417
2418 rxalign = 1;
2419 /*
2420 * Workaround hardware hang which seems to happen when Rx buffer
2421 * is not aligned on multiple of FIFO word(8 bytes).
2422 */
2423 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2424 rxalign = MSK_RX_BUF_ALIGN;
2425 /* Create tag for jumbo Rx buffers. */
2426 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2427 rxalign, 0, /* alignment, boundary */
2428 BUS_SPACE_MAXADDR, /* lowaddr */
2429 BUS_SPACE_MAXADDR, /* highaddr */
2430 NULL, NULL, /* filter, filterarg */
2431 MJUM9BYTES, /* maxsize */
2432 1, /* nsegments */
2433 MJUM9BYTES, /* maxsegsize */
2434 0, /* flags */
2435 NULL, NULL, /* lockfunc, lockarg */
2436 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2437 if (error != 0) {
2438 device_printf(sc_if->msk_if_dev,
2439 "failed to create jumbo Rx DMA tag\n");
2440 goto jumbo_fail;
2441 }
2442
2443 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2444 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2445 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2446 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2447 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2448 if (error != 0) {
2449 device_printf(sc_if->msk_if_dev,
2450 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2451 goto jumbo_fail;
2452 }
2453
2454 ctx.msk_busaddr = 0;
2455 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2456 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2457 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2458 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2459 if (error != 0) {
2460 device_printf(sc_if->msk_if_dev,
2461 "failed to load DMA'able memory for jumbo Rx ring\n");
2462 goto jumbo_fail;
2463 }
2464 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2465
2466 /* Create DMA maps for jumbo Rx buffers. */
2467 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2468 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2469 device_printf(sc_if->msk_if_dev,
2470 "failed to create spare jumbo Rx dmamap\n");
2471 goto jumbo_fail;
2472 }
2473 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2474 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2475 jrxd->rx_m = NULL;
2476 jrxd->rx_dmamap = NULL;
2477 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2478 &jrxd->rx_dmamap);
2479 if (error != 0) {
2480 device_printf(sc_if->msk_if_dev,
2481 "failed to create jumbo Rx dmamap\n");
2482 goto jumbo_fail;
2483 }
2484 }
2485
2486 return (0);
2487
2488 jumbo_fail:
2489 msk_rx_dma_jfree(sc_if);
2490 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2491 "due to resource shortage\n");
2492 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2493 return (error);
2494 }
2495
2496 static void
msk_txrx_dma_free(struct msk_if_softc * sc_if)2497 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2498 {
2499 struct msk_txdesc *txd;
2500 struct msk_rxdesc *rxd;
2501 int i;
2502
2503 /* Tx ring. */
2504 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2505 if (sc_if->msk_rdata.msk_tx_ring_paddr)
2506 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2507 sc_if->msk_cdata.msk_tx_ring_map);
2508 if (sc_if->msk_rdata.msk_tx_ring)
2509 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2510 sc_if->msk_rdata.msk_tx_ring,
2511 sc_if->msk_cdata.msk_tx_ring_map);
2512 sc_if->msk_rdata.msk_tx_ring = NULL;
2513 sc_if->msk_rdata.msk_tx_ring_paddr = 0;
2514 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2515 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2516 }
2517 /* Rx ring. */
2518 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2519 if (sc_if->msk_rdata.msk_rx_ring_paddr)
2520 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2521 sc_if->msk_cdata.msk_rx_ring_map);
2522 if (sc_if->msk_rdata.msk_rx_ring)
2523 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2524 sc_if->msk_rdata.msk_rx_ring,
2525 sc_if->msk_cdata.msk_rx_ring_map);
2526 sc_if->msk_rdata.msk_rx_ring = NULL;
2527 sc_if->msk_rdata.msk_rx_ring_paddr = 0;
2528 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2529 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2530 }
2531 /* Tx buffers. */
2532 if (sc_if->msk_cdata.msk_tx_tag) {
2533 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2534 txd = &sc_if->msk_cdata.msk_txdesc[i];
2535 if (txd->tx_dmamap) {
2536 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2537 txd->tx_dmamap);
2538 txd->tx_dmamap = NULL;
2539 }
2540 }
2541 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2542 sc_if->msk_cdata.msk_tx_tag = NULL;
2543 }
2544 /* Rx buffers. */
2545 if (sc_if->msk_cdata.msk_rx_tag) {
2546 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2547 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2548 if (rxd->rx_dmamap) {
2549 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2550 rxd->rx_dmamap);
2551 rxd->rx_dmamap = NULL;
2552 }
2553 }
2554 if (sc_if->msk_cdata.msk_rx_sparemap) {
2555 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2556 sc_if->msk_cdata.msk_rx_sparemap);
2557 sc_if->msk_cdata.msk_rx_sparemap = 0;
2558 }
2559 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2560 sc_if->msk_cdata.msk_rx_tag = NULL;
2561 }
2562 if (sc_if->msk_cdata.msk_parent_tag) {
2563 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2564 sc_if->msk_cdata.msk_parent_tag = NULL;
2565 }
2566 }
2567
2568 static void
msk_rx_dma_jfree(struct msk_if_softc * sc_if)2569 msk_rx_dma_jfree(struct msk_if_softc *sc_if)
2570 {
2571 struct msk_rxdesc *jrxd;
2572 int i;
2573
2574 /* Jumbo Rx ring. */
2575 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2576 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr)
2577 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2578 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2579 if (sc_if->msk_rdata.msk_jumbo_rx_ring)
2580 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2581 sc_if->msk_rdata.msk_jumbo_rx_ring,
2582 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2583 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2584 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0;
2585 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2586 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2587 }
2588 /* Jumbo Rx buffers. */
2589 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2590 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2591 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2592 if (jrxd->rx_dmamap) {
2593 bus_dmamap_destroy(
2594 sc_if->msk_cdata.msk_jumbo_rx_tag,
2595 jrxd->rx_dmamap);
2596 jrxd->rx_dmamap = NULL;
2597 }
2598 }
2599 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2600 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2601 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2602 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2603 }
2604 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2605 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2606 }
2607 }
2608
2609 static int
msk_encap(struct msk_if_softc * sc_if,struct mbuf ** m_head)2610 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2611 {
2612 struct msk_txdesc *txd, *txd_last;
2613 struct msk_tx_desc *tx_le;
2614 struct mbuf *m;
2615 bus_dmamap_t map;
2616 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2617 uint32_t control, csum, prod, si;
2618 uint16_t offset, tcp_offset, tso_mtu;
2619 int error, i, nseg, tso;
2620
2621 MSK_IF_LOCK_ASSERT(sc_if);
2622
2623 tcp_offset = offset = 0;
2624 m = *m_head;
2625 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2626 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2627 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2628 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2629 /*
2630 * Since mbuf has no protocol specific structure information
2631 * in it we have to inspect protocol information here to
2632 * setup TSO and checksum offload. I don't know why Marvell
2633 * made a such decision in chip design because other GigE
2634 * hardwares normally takes care of all these chores in
2635 * hardware. However, TSO performance of Yukon II is very
2636 * good such that it's worth to implement it.
2637 */
2638 struct ether_header *eh;
2639 struct ip *ip;
2640 struct tcphdr *tcp;
2641
2642 if (M_WRITABLE(m) == 0) {
2643 /* Get a writable copy. */
2644 m = m_dup(*m_head, M_NOWAIT);
2645 m_freem(*m_head);
2646 if (m == NULL) {
2647 *m_head = NULL;
2648 return (ENOBUFS);
2649 }
2650 *m_head = m;
2651 }
2652
2653 offset = sizeof(struct ether_header);
2654 m = m_pullup(m, offset);
2655 if (m == NULL) {
2656 *m_head = NULL;
2657 return (ENOBUFS);
2658 }
2659 eh = mtod(m, struct ether_header *);
2660 /* Check if hardware VLAN insertion is off. */
2661 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2662 offset = sizeof(struct ether_vlan_header);
2663 m = m_pullup(m, offset);
2664 if (m == NULL) {
2665 *m_head = NULL;
2666 return (ENOBUFS);
2667 }
2668 }
2669 m = m_pullup(m, offset + sizeof(struct ip));
2670 if (m == NULL) {
2671 *m_head = NULL;
2672 return (ENOBUFS);
2673 }
2674 ip = (struct ip *)(mtod(m, char *) + offset);
2675 offset += (ip->ip_hl << 2);
2676 tcp_offset = offset;
2677 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2678 m = m_pullup(m, offset + sizeof(struct tcphdr));
2679 if (m == NULL) {
2680 *m_head = NULL;
2681 return (ENOBUFS);
2682 }
2683 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2684 offset += (tcp->th_off << 2);
2685 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2686 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2687 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2688 /*
2689 * It seems that Yukon II has Tx checksum offload bug
2690 * for small TCP packets that's less than 60 bytes in
2691 * size (e.g. TCP window probe packet, pure ACK packet).
2692 * Common work around like padding with zeros to make
2693 * the frame minimum ethernet frame size didn't work at
2694 * all.
2695 * Instead of disabling checksum offload completely we
2696 * resort to S/W checksum routine when we encounter
2697 * short TCP frames.
2698 * Short UDP packets appear to be handled correctly by
2699 * Yukon II. Also I assume this bug does not happen on
2700 * controllers that use newer descriptor format or
2701 * automatic Tx checksum calculation.
2702 */
2703 m = m_pullup(m, offset + sizeof(struct tcphdr));
2704 if (m == NULL) {
2705 *m_head = NULL;
2706 return (ENOBUFS);
2707 }
2708 *(uint16_t *)(m->m_data + offset +
2709 m->m_pkthdr.csum_data) = in_cksum_skip(m,
2710 m->m_pkthdr.len, offset);
2711 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2712 }
2713 *m_head = m;
2714 }
2715
2716 prod = sc_if->msk_cdata.msk_tx_prod;
2717 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2718 txd_last = txd;
2719 map = txd->tx_dmamap;
2720 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2721 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2722 if (error == EFBIG) {
2723 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS);
2724 if (m == NULL) {
2725 m_freem(*m_head);
2726 *m_head = NULL;
2727 return (ENOBUFS);
2728 }
2729 *m_head = m;
2730 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2731 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2732 if (error != 0) {
2733 m_freem(*m_head);
2734 *m_head = NULL;
2735 return (error);
2736 }
2737 } else if (error != 0)
2738 return (error);
2739 if (nseg == 0) {
2740 m_freem(*m_head);
2741 *m_head = NULL;
2742 return (EIO);
2743 }
2744
2745 /* Check number of available descriptors. */
2746 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2747 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2748 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2749 return (ENOBUFS);
2750 }
2751
2752 control = 0;
2753 tso = 0;
2754 tx_le = NULL;
2755
2756 /* Check TSO support. */
2757 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2758 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2759 tso_mtu = m->m_pkthdr.tso_segsz;
2760 else
2761 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2762 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2763 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2764 tx_le->msk_addr = htole32(tso_mtu);
2765 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2766 tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2767 else
2768 tx_le->msk_control =
2769 htole32(OP_LRGLEN | HW_OWNER);
2770 sc_if->msk_cdata.msk_tx_cnt++;
2771 MSK_INC(prod, MSK_TX_RING_CNT);
2772 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2773 }
2774 tso++;
2775 }
2776 /* Check if we have a VLAN tag to insert. */
2777 if ((m->m_flags & M_VLANTAG) != 0) {
2778 if (tx_le == NULL) {
2779 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2780 tx_le->msk_addr = htole32(0);
2781 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2782 htons(m->m_pkthdr.ether_vtag));
2783 sc_if->msk_cdata.msk_tx_cnt++;
2784 MSK_INC(prod, MSK_TX_RING_CNT);
2785 } else {
2786 tx_le->msk_control |= htole32(OP_VLAN |
2787 htons(m->m_pkthdr.ether_vtag));
2788 }
2789 control |= INS_VLAN;
2790 }
2791 /* Check if we have to handle checksum offload. */
2792 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2793 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2794 control |= CALSUM;
2795 else {
2796 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2797 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2798 control |= UDPTCP;
2799 /* Checksum write position. */
2800 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2801 /* Checksum start position. */
2802 csum |= (uint32_t)tcp_offset << 16;
2803 if (csum != sc_if->msk_cdata.msk_last_csum) {
2804 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2805 tx_le->msk_addr = htole32(csum);
2806 tx_le->msk_control = htole32(1 << 16 |
2807 (OP_TCPLISW | HW_OWNER));
2808 sc_if->msk_cdata.msk_tx_cnt++;
2809 MSK_INC(prod, MSK_TX_RING_CNT);
2810 sc_if->msk_cdata.msk_last_csum = csum;
2811 }
2812 }
2813 }
2814
2815 #ifdef MSK_64BIT_DMA
2816 if (MSK_ADDR_HI(txsegs[0].ds_addr) !=
2817 sc_if->msk_cdata.msk_tx_high_addr) {
2818 sc_if->msk_cdata.msk_tx_high_addr =
2819 MSK_ADDR_HI(txsegs[0].ds_addr);
2820 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2821 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2822 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2823 sc_if->msk_cdata.msk_tx_cnt++;
2824 MSK_INC(prod, MSK_TX_RING_CNT);
2825 }
2826 #endif
2827 si = prod;
2828 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2829 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2830 if (tso == 0)
2831 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2832 OP_PACKET);
2833 else
2834 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2835 OP_LARGESEND);
2836 sc_if->msk_cdata.msk_tx_cnt++;
2837 MSK_INC(prod, MSK_TX_RING_CNT);
2838
2839 for (i = 1; i < nseg; i++) {
2840 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2841 #ifdef MSK_64BIT_DMA
2842 if (MSK_ADDR_HI(txsegs[i].ds_addr) !=
2843 sc_if->msk_cdata.msk_tx_high_addr) {
2844 sc_if->msk_cdata.msk_tx_high_addr =
2845 MSK_ADDR_HI(txsegs[i].ds_addr);
2846 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2847 tx_le->msk_addr =
2848 htole32(MSK_ADDR_HI(txsegs[i].ds_addr));
2849 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2850 sc_if->msk_cdata.msk_tx_cnt++;
2851 MSK_INC(prod, MSK_TX_RING_CNT);
2852 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2853 }
2854 #endif
2855 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2856 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2857 OP_BUFFER | HW_OWNER);
2858 sc_if->msk_cdata.msk_tx_cnt++;
2859 MSK_INC(prod, MSK_TX_RING_CNT);
2860 }
2861 /* Update producer index. */
2862 sc_if->msk_cdata.msk_tx_prod = prod;
2863
2864 /* Set EOP on the last descriptor. */
2865 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2866 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2867 tx_le->msk_control |= htole32(EOP);
2868
2869 /* Turn the first descriptor ownership to hardware. */
2870 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2871 tx_le->msk_control |= htole32(HW_OWNER);
2872
2873 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2874 map = txd_last->tx_dmamap;
2875 txd_last->tx_dmamap = txd->tx_dmamap;
2876 txd->tx_dmamap = map;
2877 txd->tx_m = m;
2878
2879 /* Sync descriptors. */
2880 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2881 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2882 sc_if->msk_cdata.msk_tx_ring_map,
2883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2884
2885 return (0);
2886 }
2887
2888 static void
msk_start(if_t ifp)2889 msk_start(if_t ifp)
2890 {
2891 struct msk_if_softc *sc_if;
2892
2893 sc_if = if_getsoftc(ifp);
2894 MSK_IF_LOCK(sc_if);
2895 msk_start_locked(ifp);
2896 MSK_IF_UNLOCK(sc_if);
2897 }
2898
2899 static void
msk_start_locked(if_t ifp)2900 msk_start_locked(if_t ifp)
2901 {
2902 struct msk_if_softc *sc_if;
2903 struct mbuf *m_head;
2904 int enq;
2905
2906 sc_if = if_getsoftc(ifp);
2907 MSK_IF_LOCK_ASSERT(sc_if);
2908
2909 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2910 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2911 return;
2912
2913 for (enq = 0; !if_sendq_empty(ifp) &&
2914 sc_if->msk_cdata.msk_tx_cnt <
2915 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2916 m_head = if_dequeue(ifp);
2917 if (m_head == NULL)
2918 break;
2919 /*
2920 * Pack the data into the transmit ring. If we
2921 * don't have room, set the OACTIVE flag and wait
2922 * for the NIC to drain the ring.
2923 */
2924 if (msk_encap(sc_if, &m_head) != 0) {
2925 if (m_head == NULL)
2926 break;
2927 if_sendq_prepend(ifp, m_head);
2928 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2929 break;
2930 }
2931
2932 enq++;
2933 /*
2934 * If there's a BPF listener, bounce a copy of this frame
2935 * to him.
2936 */
2937 ETHER_BPF_MTAP(ifp, m_head);
2938 }
2939
2940 if (enq > 0) {
2941 /* Transmit */
2942 CSR_WRITE_2(sc_if->msk_softc,
2943 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2944 sc_if->msk_cdata.msk_tx_prod);
2945
2946 /* Set a timeout in case the chip goes out to lunch. */
2947 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2948 }
2949 }
2950
2951 static void
msk_watchdog(struct msk_if_softc * sc_if)2952 msk_watchdog(struct msk_if_softc *sc_if)
2953 {
2954 if_t ifp;
2955
2956 MSK_IF_LOCK_ASSERT(sc_if);
2957
2958 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2959 return;
2960 ifp = sc_if->msk_ifp;
2961 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2962 if (bootverbose)
2963 if_printf(sc_if->msk_ifp, "watchdog timeout "
2964 "(missed link)\n");
2965 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2966 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2967 msk_init_locked(sc_if);
2968 return;
2969 }
2970
2971 if_printf(ifp, "watchdog timeout\n");
2972 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2973 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2974 msk_init_locked(sc_if);
2975 if (!if_sendq_empty(ifp))
2976 msk_start_locked(ifp);
2977 }
2978
2979 static int
mskc_shutdown(device_t dev)2980 mskc_shutdown(device_t dev)
2981 {
2982 struct msk_softc *sc;
2983 int i;
2984
2985 sc = device_get_softc(dev);
2986 MSK_LOCK(sc);
2987 for (i = 0; i < sc->msk_num_port; i++) {
2988 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2989 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
2990 IFF_DRV_RUNNING) != 0))
2991 msk_stop(sc->msk_if[i]);
2992 }
2993 MSK_UNLOCK(sc);
2994
2995 /* Put hardware reset. */
2996 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2997 return (0);
2998 }
2999
3000 static int
mskc_suspend(device_t dev)3001 mskc_suspend(device_t dev)
3002 {
3003 struct msk_softc *sc;
3004 int i;
3005
3006 sc = device_get_softc(dev);
3007
3008 MSK_LOCK(sc);
3009
3010 for (i = 0; i < sc->msk_num_port; i++) {
3011 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3012 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
3013 IFF_DRV_RUNNING) != 0))
3014 msk_stop(sc->msk_if[i]);
3015 }
3016
3017 /* Disable all interrupts. */
3018 CSR_WRITE_4(sc, B0_IMSK, 0);
3019 CSR_READ_4(sc, B0_IMSK);
3020 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3021 CSR_READ_4(sc, B0_HWE_IMSK);
3022
3023 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3024
3025 /* Put hardware reset. */
3026 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3027 sc->msk_pflags |= MSK_FLAG_SUSPEND;
3028
3029 MSK_UNLOCK(sc);
3030
3031 return (0);
3032 }
3033
3034 static int
mskc_resume(device_t dev)3035 mskc_resume(device_t dev)
3036 {
3037 struct msk_softc *sc;
3038 int i;
3039
3040 sc = device_get_softc(dev);
3041
3042 MSK_LOCK(sc);
3043
3044 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
3045 mskc_reset(sc);
3046 for (i = 0; i < sc->msk_num_port; i++) {
3047 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3048 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) {
3049 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0,
3050 IFF_DRV_RUNNING);
3051 msk_init_locked(sc->msk_if[i]);
3052 }
3053 }
3054 sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3055
3056 MSK_UNLOCK(sc);
3057
3058 return (0);
3059 }
3060
3061 #ifndef __NO_STRICT_ALIGNMENT
3062 static __inline void
msk_fixup_rx(struct mbuf * m)3063 msk_fixup_rx(struct mbuf *m)
3064 {
3065 int i;
3066 uint16_t *src, *dst;
3067
3068 src = mtod(m, uint16_t *);
3069 dst = src - 3;
3070
3071 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3072 *dst++ = *src++;
3073
3074 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3075 }
3076 #endif
3077
3078 static __inline void
msk_rxcsum(struct msk_if_softc * sc_if,uint32_t control,struct mbuf * m)3079 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3080 {
3081 struct ether_header *eh;
3082 struct ip *ip;
3083 struct udphdr *uh;
3084 int32_t hlen, len, pktlen, temp32;
3085 uint16_t csum, *opts;
3086
3087 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3088 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3089 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3090 if ((control & CSS_IPV4_CSUM_OK) != 0)
3091 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3092 if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3093 (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3094 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3095 CSUM_PSEUDO_HDR;
3096 m->m_pkthdr.csum_data = 0xffff;
3097 }
3098 }
3099 return;
3100 }
3101 /*
3102 * Marvell Yukon controllers that support OP_RXCHKS has known
3103 * to have various Rx checksum offloading bugs. These
3104 * controllers can be configured to compute simple checksum
3105 * at two different positions. So we can compute IP and TCP/UDP
3106 * checksum at the same time. We intentionally have controller
3107 * compute TCP/UDP checksum twice by specifying the same
3108 * checksum start position and compare the result. If the value
3109 * is different it would indicate the hardware logic was wrong.
3110 */
3111 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3112 if (bootverbose)
3113 device_printf(sc_if->msk_if_dev,
3114 "Rx checksum value mismatch!\n");
3115 return;
3116 }
3117 pktlen = m->m_pkthdr.len;
3118 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3119 return;
3120 eh = mtod(m, struct ether_header *);
3121 if (eh->ether_type != htons(ETHERTYPE_IP))
3122 return;
3123 ip = (struct ip *)(eh + 1);
3124 if (ip->ip_v != IPVERSION)
3125 return;
3126
3127 hlen = ip->ip_hl << 2;
3128 pktlen -= sizeof(struct ether_header);
3129 if (hlen < sizeof(struct ip))
3130 return;
3131 if (ntohs(ip->ip_len) < hlen)
3132 return;
3133 if (ntohs(ip->ip_len) != pktlen)
3134 return;
3135 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3136 return; /* can't handle fragmented packet. */
3137
3138 switch (ip->ip_p) {
3139 case IPPROTO_TCP:
3140 if (pktlen < (hlen + sizeof(struct tcphdr)))
3141 return;
3142 break;
3143 case IPPROTO_UDP:
3144 if (pktlen < (hlen + sizeof(struct udphdr)))
3145 return;
3146 uh = (struct udphdr *)((caddr_t)ip + hlen);
3147 if (uh->uh_sum == 0)
3148 return; /* no checksum */
3149 break;
3150 default:
3151 return;
3152 }
3153 csum = bswap16(sc_if->msk_csum & 0xFFFF);
3154 /* Checksum fixup for IP options. */
3155 len = hlen - sizeof(struct ip);
3156 if (len > 0) {
3157 opts = (uint16_t *)(ip + 1);
3158 for (; len > 0; len -= sizeof(uint16_t), opts++) {
3159 temp32 = csum - *opts;
3160 temp32 = (temp32 >> 16) + (temp32 & 65535);
3161 csum = temp32 & 65535;
3162 }
3163 }
3164 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3165 m->m_pkthdr.csum_data = csum;
3166 }
3167
3168 static void
msk_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3169 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3170 int len)
3171 {
3172 struct mbuf *m;
3173 if_t ifp;
3174 struct msk_rxdesc *rxd;
3175 int cons, rxlen;
3176
3177 ifp = sc_if->msk_ifp;
3178
3179 MSK_IF_LOCK_ASSERT(sc_if);
3180
3181 cons = sc_if->msk_cdata.msk_rx_cons;
3182 do {
3183 rxlen = status >> 16;
3184 if ((status & GMR_FS_VLAN) != 0 &&
3185 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3186 rxlen -= ETHER_VLAN_ENCAP_LEN;
3187 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3188 /*
3189 * For controllers that returns bogus status code
3190 * just do minimal check and let upper stack
3191 * handle this frame.
3192 */
3193 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3194 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3195 msk_discard_rxbuf(sc_if, cons);
3196 break;
3197 }
3198 } else if (len > sc_if->msk_framesize ||
3199 ((status & GMR_FS_ANY_ERR) != 0) ||
3200 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3201 /* Don't count flow-control packet as errors. */
3202 if ((status & GMR_FS_GOOD_FC) == 0)
3203 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3204 msk_discard_rxbuf(sc_if, cons);
3205 break;
3206 }
3207 #ifdef MSK_64BIT_DMA
3208 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3209 MSK_RX_RING_CNT];
3210 #else
3211 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3212 #endif
3213 m = rxd->rx_m;
3214 if (msk_newbuf(sc_if, cons) != 0) {
3215 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3216 /* Reuse old buffer. */
3217 msk_discard_rxbuf(sc_if, cons);
3218 break;
3219 }
3220 m->m_pkthdr.rcvif = ifp;
3221 m->m_pkthdr.len = m->m_len = len;
3222 #ifndef __NO_STRICT_ALIGNMENT
3223 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3224 msk_fixup_rx(m);
3225 #endif
3226 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3227 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3228 msk_rxcsum(sc_if, control, m);
3229 /* Check for VLAN tagged packets. */
3230 if ((status & GMR_FS_VLAN) != 0 &&
3231 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3232 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3233 m->m_flags |= M_VLANTAG;
3234 }
3235 MSK_IF_UNLOCK(sc_if);
3236 if_input(ifp, m);
3237 MSK_IF_LOCK(sc_if);
3238 } while (0);
3239
3240 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3241 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3242 }
3243
3244 static void
msk_jumbo_rxeof(struct msk_if_softc * sc_if,uint32_t status,uint32_t control,int len)3245 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3246 int len)
3247 {
3248 struct mbuf *m;
3249 if_t ifp;
3250 struct msk_rxdesc *jrxd;
3251 int cons, rxlen;
3252
3253 ifp = sc_if->msk_ifp;
3254
3255 MSK_IF_LOCK_ASSERT(sc_if);
3256
3257 cons = sc_if->msk_cdata.msk_rx_cons;
3258 do {
3259 rxlen = status >> 16;
3260 if ((status & GMR_FS_VLAN) != 0 &&
3261 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3262 rxlen -= ETHER_VLAN_ENCAP_LEN;
3263 if (len > sc_if->msk_framesize ||
3264 ((status & GMR_FS_ANY_ERR) != 0) ||
3265 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3266 /* Don't count flow-control packet as errors. */
3267 if ((status & GMR_FS_GOOD_FC) == 0)
3268 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3269 msk_discard_jumbo_rxbuf(sc_if, cons);
3270 break;
3271 }
3272 #ifdef MSK_64BIT_DMA
3273 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3274 MSK_JUMBO_RX_RING_CNT];
3275 #else
3276 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3277 #endif
3278 m = jrxd->rx_m;
3279 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3280 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3281 /* Reuse old buffer. */
3282 msk_discard_jumbo_rxbuf(sc_if, cons);
3283 break;
3284 }
3285 m->m_pkthdr.rcvif = ifp;
3286 m->m_pkthdr.len = m->m_len = len;
3287 #ifndef __NO_STRICT_ALIGNMENT
3288 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3289 msk_fixup_rx(m);
3290 #endif
3291 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3292 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3293 msk_rxcsum(sc_if, control, m);
3294 /* Check for VLAN tagged packets. */
3295 if ((status & GMR_FS_VLAN) != 0 &&
3296 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3297 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3298 m->m_flags |= M_VLANTAG;
3299 }
3300 MSK_IF_UNLOCK(sc_if);
3301 if_input(ifp, m);
3302 MSK_IF_LOCK(sc_if);
3303 } while (0);
3304
3305 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3306 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3307 }
3308
3309 static void
msk_txeof(struct msk_if_softc * sc_if,int idx)3310 msk_txeof(struct msk_if_softc *sc_if, int idx)
3311 {
3312 struct msk_txdesc *txd;
3313 struct msk_tx_desc *cur_tx;
3314 if_t ifp;
3315 uint32_t control;
3316 int cons, prog;
3317
3318 MSK_IF_LOCK_ASSERT(sc_if);
3319
3320 ifp = sc_if->msk_ifp;
3321
3322 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3323 sc_if->msk_cdata.msk_tx_ring_map,
3324 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3325 /*
3326 * Go through our tx ring and free mbufs for those
3327 * frames that have been sent.
3328 */
3329 cons = sc_if->msk_cdata.msk_tx_cons;
3330 prog = 0;
3331 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3332 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3333 break;
3334 prog++;
3335 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3336 control = le32toh(cur_tx->msk_control);
3337 sc_if->msk_cdata.msk_tx_cnt--;
3338 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3339 if ((control & EOP) == 0)
3340 continue;
3341 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3342 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3343 BUS_DMASYNC_POSTWRITE);
3344 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3345
3346 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3347 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3348 __func__));
3349 m_freem(txd->tx_m);
3350 txd->tx_m = NULL;
3351 }
3352
3353 if (prog > 0) {
3354 sc_if->msk_cdata.msk_tx_cons = cons;
3355 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3356 sc_if->msk_watchdog_timer = 0;
3357 /* No need to sync LEs as we didn't update LEs. */
3358 }
3359 }
3360
3361 static void
msk_tick(void * xsc_if)3362 msk_tick(void *xsc_if)
3363 {
3364 struct epoch_tracker et;
3365 struct msk_if_softc *sc_if;
3366 struct mii_data *mii;
3367
3368 sc_if = xsc_if;
3369
3370 MSK_IF_LOCK_ASSERT(sc_if);
3371
3372 mii = device_get_softc(sc_if->msk_miibus);
3373
3374 mii_tick(mii);
3375 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3376 msk_miibus_statchg(sc_if->msk_if_dev);
3377 NET_EPOCH_ENTER(et);
3378 msk_handle_events(sc_if->msk_softc);
3379 NET_EPOCH_EXIT(et);
3380 msk_watchdog(sc_if);
3381 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3382 }
3383
3384 static void
msk_intr_phy(struct msk_if_softc * sc_if)3385 msk_intr_phy(struct msk_if_softc *sc_if)
3386 {
3387 uint16_t status;
3388
3389 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3390 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3391 /* Handle FIFO Underrun/Overflow? */
3392 if ((status & PHY_M_IS_FIFO_ERROR))
3393 device_printf(sc_if->msk_if_dev,
3394 "PHY FIFO underrun/overflow.\n");
3395 }
3396
3397 static void
msk_intr_gmac(struct msk_if_softc * sc_if)3398 msk_intr_gmac(struct msk_if_softc *sc_if)
3399 {
3400 struct msk_softc *sc;
3401 uint8_t status;
3402
3403 sc = sc_if->msk_softc;
3404 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3405
3406 /* GMAC Rx FIFO overrun. */
3407 if ((status & GM_IS_RX_FF_OR) != 0)
3408 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3409 GMF_CLI_RX_FO);
3410 /* GMAC Tx FIFO underrun. */
3411 if ((status & GM_IS_TX_FF_UR) != 0) {
3412 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3413 GMF_CLI_TX_FU);
3414 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3415 /*
3416 * XXX
3417 * In case of Tx underrun, we may need to flush/reset
3418 * Tx MAC but that would also require resynchronization
3419 * with status LEs. Reinitializing status LEs would
3420 * affect other port in dual MAC configuration so it
3421 * should be avoided as possible as we can.
3422 * Due to lack of documentation it's all vague guess but
3423 * it needs more investigation.
3424 */
3425 }
3426 }
3427
3428 static void
msk_handle_hwerr(struct msk_if_softc * sc_if,uint32_t status)3429 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3430 {
3431 struct msk_softc *sc;
3432
3433 sc = sc_if->msk_softc;
3434 if ((status & Y2_IS_PAR_RD1) != 0) {
3435 device_printf(sc_if->msk_if_dev,
3436 "RAM buffer read parity error\n");
3437 /* Clear IRQ. */
3438 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3439 RI_CLR_RD_PERR);
3440 }
3441 if ((status & Y2_IS_PAR_WR1) != 0) {
3442 device_printf(sc_if->msk_if_dev,
3443 "RAM buffer write parity error\n");
3444 /* Clear IRQ. */
3445 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3446 RI_CLR_WR_PERR);
3447 }
3448 if ((status & Y2_IS_PAR_MAC1) != 0) {
3449 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3450 /* Clear IRQ. */
3451 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3452 GMF_CLI_TX_PE);
3453 }
3454 if ((status & Y2_IS_PAR_RX1) != 0) {
3455 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3456 /* Clear IRQ. */
3457 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3458 }
3459 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3460 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3461 /* Clear IRQ. */
3462 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3463 }
3464 }
3465
3466 static void
msk_intr_hwerr(struct msk_softc * sc)3467 msk_intr_hwerr(struct msk_softc *sc)
3468 {
3469 uint32_t status;
3470 uint32_t tlphead[4];
3471
3472 status = CSR_READ_4(sc, B0_HWE_ISRC);
3473 /* Time Stamp timer overflow. */
3474 if ((status & Y2_IS_TIST_OV) != 0)
3475 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3476 if ((status & Y2_IS_PCI_NEXP) != 0) {
3477 /*
3478 * PCI Express Error occurred which is not described in PEX
3479 * spec.
3480 * This error is also mapped either to Master Abort(
3481 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3482 * can only be cleared there.
3483 */
3484 device_printf(sc->msk_dev,
3485 "PCI Express protocol violation error\n");
3486 }
3487
3488 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3489 uint16_t v16;
3490
3491 if ((status & Y2_IS_MST_ERR) != 0)
3492 device_printf(sc->msk_dev,
3493 "unexpected IRQ Status error\n");
3494 else
3495 device_printf(sc->msk_dev,
3496 "unexpected IRQ Master error\n");
3497 /* Reset all bits in the PCI status register. */
3498 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3499 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3500 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3501 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3502 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
3503 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3504 }
3505
3506 /* Check for PCI Express Uncorrectable Error. */
3507 if ((status & Y2_IS_PCI_EXP) != 0) {
3508 uint32_t v32;
3509
3510 /*
3511 * On PCI Express bus bridges are called root complexes (RC).
3512 * PCI Express errors are recognized by the root complex too,
3513 * which requests the system to handle the problem. After
3514 * error occurrence it may be that no access to the adapter
3515 * may be performed any longer.
3516 */
3517
3518 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3519 if ((v32 & PEX_UNSUP_REQ) != 0) {
3520 /* Ignore unsupported request error. */
3521 device_printf(sc->msk_dev,
3522 "Uncorrectable PCI Express error\n");
3523 }
3524 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3525 int i;
3526
3527 /* Get TLP header form Log Registers. */
3528 for (i = 0; i < 4; i++)
3529 tlphead[i] = CSR_PCI_READ_4(sc,
3530 PEX_HEADER_LOG + i * 4);
3531 /* Check for vendor defined broadcast message. */
3532 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3533 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3534 CSR_WRITE_4(sc, B0_HWE_IMSK,
3535 sc->msk_intrhwemask);
3536 CSR_READ_4(sc, B0_HWE_IMSK);
3537 }
3538 }
3539 /* Clear the interrupt. */
3540 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3541 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3542 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3543 }
3544
3545 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3546 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3547 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3548 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3549 }
3550
3551 static __inline void
msk_rxput(struct msk_if_softc * sc_if)3552 msk_rxput(struct msk_if_softc *sc_if)
3553 {
3554 struct msk_softc *sc;
3555
3556 sc = sc_if->msk_softc;
3557 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3558 bus_dmamap_sync(
3559 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3560 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3561 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3562 else
3563 bus_dmamap_sync(
3564 sc_if->msk_cdata.msk_rx_ring_tag,
3565 sc_if->msk_cdata.msk_rx_ring_map,
3566 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3567 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3568 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3569 }
3570
3571 static int
msk_handle_events(struct msk_softc * sc)3572 msk_handle_events(struct msk_softc *sc)
3573 {
3574 struct msk_if_softc *sc_if;
3575 int rxput[2];
3576 struct msk_stat_desc *sd;
3577 uint32_t control, status;
3578 int cons, len, port, rxprog;
3579
3580 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3581 return (0);
3582
3583 /* Sync status LEs. */
3584 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3585 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3586
3587 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3588 rxprog = 0;
3589 cons = sc->msk_stat_cons;
3590 for (;;) {
3591 sd = &sc->msk_stat_ring[cons];
3592 control = le32toh(sd->msk_control);
3593 if ((control & HW_OWNER) == 0)
3594 break;
3595 control &= ~HW_OWNER;
3596 sd->msk_control = htole32(control);
3597 status = le32toh(sd->msk_status);
3598 len = control & STLE_LEN_MASK;
3599 port = (control >> 16) & 0x01;
3600 sc_if = sc->msk_if[port];
3601 if (sc_if == NULL) {
3602 device_printf(sc->msk_dev, "invalid port opcode "
3603 "0x%08x\n", control & STLE_OP_MASK);
3604 continue;
3605 }
3606
3607 switch (control & STLE_OP_MASK) {
3608 case OP_RXVLAN:
3609 sc_if->msk_vtag = ntohs(len);
3610 break;
3611 case OP_RXCHKSVLAN:
3612 sc_if->msk_vtag = ntohs(len);
3613 /* FALLTHROUGH */
3614 case OP_RXCHKS:
3615 sc_if->msk_csum = status;
3616 break;
3617 case OP_RXSTAT:
3618 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING))
3619 break;
3620 if (sc_if->msk_framesize >
3621 (MCLBYTES - MSK_RX_BUF_ALIGN))
3622 msk_jumbo_rxeof(sc_if, status, control, len);
3623 else
3624 msk_rxeof(sc_if, status, control, len);
3625 rxprog++;
3626 /*
3627 * Because there is no way to sync single Rx LE
3628 * put the DMA sync operation off until the end of
3629 * event processing.
3630 */
3631 rxput[port]++;
3632 /* Update prefetch unit if we've passed water mark. */
3633 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3634 msk_rxput(sc_if);
3635 rxput[port] = 0;
3636 }
3637 break;
3638 case OP_TXINDEXLE:
3639 if (sc->msk_if[MSK_PORT_A] != NULL)
3640 msk_txeof(sc->msk_if[MSK_PORT_A],
3641 status & STLE_TXA1_MSKL);
3642 if (sc->msk_if[MSK_PORT_B] != NULL)
3643 msk_txeof(sc->msk_if[MSK_PORT_B],
3644 ((status & STLE_TXA2_MSKL) >>
3645 STLE_TXA2_SHIFTL) |
3646 ((len & STLE_TXA2_MSKH) <<
3647 STLE_TXA2_SHIFTH));
3648 break;
3649 default:
3650 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3651 control & STLE_OP_MASK);
3652 break;
3653 }
3654 MSK_INC(cons, sc->msk_stat_count);
3655 if (rxprog > sc->msk_process_limit)
3656 break;
3657 }
3658
3659 sc->msk_stat_cons = cons;
3660 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3661 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3662
3663 if (rxput[MSK_PORT_A] > 0)
3664 msk_rxput(sc->msk_if[MSK_PORT_A]);
3665 if (rxput[MSK_PORT_B] > 0)
3666 msk_rxput(sc->msk_if[MSK_PORT_B]);
3667
3668 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3669 }
3670
3671 static void
msk_intr(void * xsc)3672 msk_intr(void *xsc)
3673 {
3674 struct msk_softc *sc;
3675 struct msk_if_softc *sc_if0, *sc_if1;
3676 if_t ifp0, ifp1;
3677 uint32_t status;
3678 int domore;
3679
3680 sc = xsc;
3681 MSK_LOCK(sc);
3682
3683 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3684 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3685 if (status == 0 || status == 0xffffffff ||
3686 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3687 (status & sc->msk_intrmask) == 0) {
3688 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3689 MSK_UNLOCK(sc);
3690 return;
3691 }
3692
3693 sc_if0 = sc->msk_if[MSK_PORT_A];
3694 sc_if1 = sc->msk_if[MSK_PORT_B];
3695 ifp0 = ifp1 = NULL;
3696 if (sc_if0 != NULL)
3697 ifp0 = sc_if0->msk_ifp;
3698 if (sc_if1 != NULL)
3699 ifp1 = sc_if1->msk_ifp;
3700
3701 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3702 msk_intr_phy(sc_if0);
3703 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3704 msk_intr_phy(sc_if1);
3705 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3706 msk_intr_gmac(sc_if0);
3707 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3708 msk_intr_gmac(sc_if1);
3709 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3710 device_printf(sc->msk_dev, "Rx descriptor error\n");
3711 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3712 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3713 CSR_READ_4(sc, B0_IMSK);
3714 }
3715 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3716 device_printf(sc->msk_dev, "Tx descriptor error\n");
3717 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3718 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3719 CSR_READ_4(sc, B0_IMSK);
3720 }
3721 if ((status & Y2_IS_HW_ERR) != 0)
3722 msk_intr_hwerr(sc);
3723
3724 domore = msk_handle_events(sc);
3725 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
3726 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3727
3728 /* Reenable interrupts. */
3729 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3730
3731 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 &&
3732 !if_sendq_empty(ifp0))
3733 msk_start_locked(ifp0);
3734 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 &&
3735 !if_sendq_empty(ifp1))
3736 msk_start_locked(ifp1);
3737
3738 MSK_UNLOCK(sc);
3739 }
3740
3741 static void
msk_set_tx_stfwd(struct msk_if_softc * sc_if)3742 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3743 {
3744 struct msk_softc *sc;
3745 if_t ifp;
3746
3747 ifp = sc_if->msk_ifp;
3748 sc = sc_if->msk_softc;
3749 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3750 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3751 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3752 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3753 TX_STFW_ENA);
3754 } else {
3755 if (if_getmtu(ifp) > ETHERMTU) {
3756 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3757 CSR_WRITE_4(sc,
3758 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3759 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3760 /* Disable Store & Forward mode for Tx. */
3761 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3762 TX_STFW_DIS);
3763 } else {
3764 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3765 TX_STFW_ENA);
3766 }
3767 }
3768 }
3769
3770 static void
msk_init(void * xsc)3771 msk_init(void *xsc)
3772 {
3773 struct msk_if_softc *sc_if = xsc;
3774
3775 MSK_IF_LOCK(sc_if);
3776 msk_init_locked(sc_if);
3777 MSK_IF_UNLOCK(sc_if);
3778 }
3779
3780 static void
msk_init_locked(struct msk_if_softc * sc_if)3781 msk_init_locked(struct msk_if_softc *sc_if)
3782 {
3783 struct msk_softc *sc;
3784 if_t ifp;
3785 struct mii_data *mii;
3786 uint8_t *eaddr;
3787 uint16_t gmac;
3788 uint32_t reg;
3789 int error;
3790
3791 MSK_IF_LOCK_ASSERT(sc_if);
3792
3793 ifp = sc_if->msk_ifp;
3794 sc = sc_if->msk_softc;
3795 mii = device_get_softc(sc_if->msk_miibus);
3796
3797 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3798 return;
3799
3800 error = 0;
3801 /* Cancel pending I/O and free all Rx/Tx buffers. */
3802 msk_stop(sc_if);
3803
3804 if (if_getmtu(ifp) < ETHERMTU)
3805 sc_if->msk_framesize = ETHERMTU;
3806 else
3807 sc_if->msk_framesize = if_getmtu(ifp);
3808 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3809 if (if_getmtu(ifp) > ETHERMTU &&
3810 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3811 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO));
3812 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM));
3813 }
3814
3815 /* GMAC Control reset. */
3816 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3817 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3818 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3819 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3820 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3821 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3822 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3823 GMC_BYP_RETR_ON);
3824
3825 /*
3826 * Initialize GMAC first such that speed/duplex/flow-control
3827 * parameters are renegotiated when interface is brought up.
3828 */
3829 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3830
3831 /* Dummy read the Interrupt Source Register. */
3832 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3833
3834 /* Clear MIB stats. */
3835 msk_stats_clear(sc_if);
3836
3837 /* Disable FCS. */
3838 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3839
3840 /* Setup Transmit Control Register. */
3841 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3842
3843 /* Setup Transmit Flow Control Register. */
3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3845
3846 /* Setup Transmit Parameter Register. */
3847 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3848 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3849 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3850
3851 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3852 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3853
3854 if (if_getmtu(ifp) > ETHERMTU)
3855 gmac |= GM_SMOD_JUMBO_ENA;
3856 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3857
3858 /* Set station address. */
3859 eaddr = if_getlladdr(ifp);
3860 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3861 eaddr[0] | (eaddr[1] << 8));
3862 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3863 eaddr[2] | (eaddr[3] << 8));
3864 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3865 eaddr[4] | (eaddr[5] << 8));
3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3867 eaddr[0] | (eaddr[1] << 8));
3868 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3869 eaddr[2] | (eaddr[3] << 8));
3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3871 eaddr[4] | (eaddr[5] << 8));
3872
3873 /* Disable interrupts for counter overflows. */
3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3875 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3877
3878 /* Configure Rx MAC FIFO. */
3879 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3880 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3881 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3882 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3883 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3884 reg |= GMF_RX_OVER_ON;
3885 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3886
3887 /* Set receive filter. */
3888 msk_rxfilter(sc_if);
3889
3890 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3891 /* Clear flush mask - HW bug. */
3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3893 } else {
3894 /* Flush Rx MAC FIFO on any flow control or error. */
3895 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3896 GMR_FS_ANY_ERR);
3897 }
3898
3899 /*
3900 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3901 * due to hardware hang on receipt of pause frames.
3902 */
3903 reg = RX_GMF_FL_THR_DEF + 1;
3904 /* Another magic for Yukon FE+ - From Linux. */
3905 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3906 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3907 reg = 0x178;
3908 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3909
3910 /* Configure Tx MAC FIFO. */
3911 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3912 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3913 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3914
3915 /* Configure hardware VLAN tag insertion/stripping. */
3916 msk_setvlan(sc_if, ifp);
3917
3918 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3919 /* Set Rx Pause threshold. */
3920 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3921 MSK_ECU_LLPP);
3922 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3923 MSK_ECU_ULPP);
3924 /* Configure store-and-forward for Tx. */
3925 msk_set_tx_stfwd(sc_if);
3926 }
3927
3928 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3929 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3930 /* Disable dynamic watermark - from Linux. */
3931 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3932 reg &= ~0x03;
3933 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3934 }
3935
3936 /*
3937 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3938 * arbiter as we don't use Sync Tx queue.
3939 */
3940 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3941 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3942 /* Enable the RAM Interface Arbiter. */
3943 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3944
3945 /* Setup RAM buffer. */
3946 msk_set_rambuffer(sc_if);
3947
3948 /* Disable Tx sync Queue. */
3949 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3950
3951 /* Setup Tx Queue Bus Memory Interface. */
3952 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3953 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3954 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3955 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3956 switch (sc->msk_hw_id) {
3957 case CHIP_ID_YUKON_EC_U:
3958 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3959 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3960 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3961 MSK_ECU_TXFF_LEV);
3962 }
3963 break;
3964 case CHIP_ID_YUKON_EX:
3965 /*
3966 * Yukon Extreme seems to have silicon bug for
3967 * automatic Tx checksum calculation capability.
3968 */
3969 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3970 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3971 F_TX_CHK_AUTO_OFF);
3972 break;
3973 }
3974
3975 /* Setup Rx Queue Bus Memory Interface. */
3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3978 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3979 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3980 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3981 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3982 /* MAC Rx RAM Read is controlled by hardware. */
3983 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3984 }
3985
3986 msk_set_prefetch(sc, sc_if->msk_txq,
3987 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3988 msk_init_tx_ring(sc_if);
3989
3990 /* Disable Rx checksum offload and RSS hash. */
3991 reg = BMU_DIS_RX_RSS_HASH;
3992 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3993 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
3994 reg |= BMU_ENA_RX_CHKSUM;
3995 else
3996 reg |= BMU_DIS_RX_CHKSUM;
3997 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
3998 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
3999 msk_set_prefetch(sc, sc_if->msk_rxq,
4000 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
4001 MSK_JUMBO_RX_RING_CNT - 1);
4002 error = msk_init_jumbo_rx_ring(sc_if);
4003 } else {
4004 msk_set_prefetch(sc, sc_if->msk_rxq,
4005 sc_if->msk_rdata.msk_rx_ring_paddr,
4006 MSK_RX_RING_CNT - 1);
4007 error = msk_init_rx_ring(sc_if);
4008 }
4009 if (error != 0) {
4010 device_printf(sc_if->msk_if_dev,
4011 "initialization failed: no memory for Rx buffers\n");
4012 msk_stop(sc_if);
4013 return;
4014 }
4015 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
4016 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
4017 /* Disable flushing of non-ASF packets. */
4018 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4019 GMF_RX_MACSEC_FLUSH_OFF);
4020 }
4021
4022 /* Configure interrupt handling. */
4023 if (sc_if->msk_port == MSK_PORT_A) {
4024 sc->msk_intrmask |= Y2_IS_PORT_A;
4025 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4026 } else {
4027 sc->msk_intrmask |= Y2_IS_PORT_B;
4028 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4029 }
4030 /* Configure IRQ moderation mask. */
4031 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4032 if (sc->msk_int_holdoff > 0) {
4033 /* Configure initial IRQ moderation timer value. */
4034 CSR_WRITE_4(sc, B2_IRQM_INI,
4035 MSK_USECS(sc, sc->msk_int_holdoff));
4036 CSR_WRITE_4(sc, B2_IRQM_VAL,
4037 MSK_USECS(sc, sc->msk_int_holdoff));
4038 /* Start IRQ moderation. */
4039 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
4040 }
4041 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4042 CSR_READ_4(sc, B0_HWE_IMSK);
4043 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4044 CSR_READ_4(sc, B0_IMSK);
4045
4046 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
4047 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4048
4049 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4050 mii_mediachg(mii);
4051
4052 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4053 }
4054
4055 static void
msk_set_rambuffer(struct msk_if_softc * sc_if)4056 msk_set_rambuffer(struct msk_if_softc *sc_if)
4057 {
4058 struct msk_softc *sc;
4059 int ltpp, utpp;
4060
4061 sc = sc_if->msk_softc;
4062 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4063 return;
4064
4065 /* Setup Rx Queue. */
4066 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4067 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4068 sc->msk_rxqstart[sc_if->msk_port] / 8);
4069 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4070 sc->msk_rxqend[sc_if->msk_port] / 8);
4071 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4072 sc->msk_rxqstart[sc_if->msk_port] / 8);
4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4074 sc->msk_rxqstart[sc_if->msk_port] / 8);
4075
4076 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4077 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4078 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4079 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4080 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4081 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4082 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4083 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4084 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
4085
4086 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4087 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4088
4089 /* Setup Tx Queue. */
4090 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4091 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4092 sc->msk_txqstart[sc_if->msk_port] / 8);
4093 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4094 sc->msk_txqend[sc_if->msk_port] / 8);
4095 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4096 sc->msk_txqstart[sc_if->msk_port] / 8);
4097 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4098 sc->msk_txqstart[sc_if->msk_port] / 8);
4099 /* Enable Store & Forward for Tx side. */
4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4101 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4102 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4103 }
4104
4105 static void
msk_set_prefetch(struct msk_softc * sc,int qaddr,bus_addr_t addr,uint32_t count)4106 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
4107 uint32_t count)
4108 {
4109
4110 /* Reset the prefetch unit. */
4111 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4112 PREF_UNIT_RST_SET);
4113 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4114 PREF_UNIT_RST_CLR);
4115 /* Set LE base address. */
4116 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4117 MSK_ADDR_LO(addr));
4118 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4119 MSK_ADDR_HI(addr));
4120 /* Set the list last index. */
4121 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
4122 count);
4123 /* Turn on prefetch unit. */
4124 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4125 PREF_UNIT_OP_ON);
4126 /* Dummy read to ensure write. */
4127 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
4128 }
4129
4130 static void
msk_stop(struct msk_if_softc * sc_if)4131 msk_stop(struct msk_if_softc *sc_if)
4132 {
4133 struct msk_softc *sc;
4134 struct msk_txdesc *txd;
4135 struct msk_rxdesc *rxd;
4136 struct msk_rxdesc *jrxd;
4137 if_t ifp;
4138 uint32_t val;
4139 int i;
4140
4141 MSK_IF_LOCK_ASSERT(sc_if);
4142 sc = sc_if->msk_softc;
4143 ifp = sc_if->msk_ifp;
4144
4145 callout_stop(&sc_if->msk_tick_ch);
4146 sc_if->msk_watchdog_timer = 0;
4147
4148 /* Disable interrupts. */
4149 if (sc_if->msk_port == MSK_PORT_A) {
4150 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4151 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4152 } else {
4153 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4154 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4155 }
4156 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4157 CSR_READ_4(sc, B0_HWE_IMSK);
4158 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4159 CSR_READ_4(sc, B0_IMSK);
4160
4161 /* Disable Tx/Rx MAC. */
4162 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4163 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4164 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4165 /* Read again to ensure writing. */
4166 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4167 /* Update stats and clear counters. */
4168 msk_stats_update(sc_if);
4169
4170 /* Stop Tx BMU. */
4171 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4172 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4173 for (i = 0; i < MSK_TIMEOUT; i++) {
4174 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4175 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4176 BMU_STOP);
4177 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4178 } else
4179 break;
4180 DELAY(1);
4181 }
4182 if (i == MSK_TIMEOUT)
4183 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4184 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4185 RB_RST_SET | RB_DIS_OP_MD);
4186
4187 /* Disable all GMAC interrupt. */
4188 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4189 /* Disable PHY interrupt. */
4190 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4191
4192 /* Disable the RAM Interface Arbiter. */
4193 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4194
4195 /* Reset the PCI FIFO of the async Tx queue */
4196 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4197 BMU_RST_SET | BMU_FIFO_RST);
4198
4199 /* Reset the Tx prefetch units. */
4200 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4201 PREF_UNIT_RST_SET);
4202
4203 /* Reset the RAM Buffer async Tx queue. */
4204 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4205
4206 /* Reset Tx MAC FIFO. */
4207 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4208 /* Set Pause Off. */
4209 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4210
4211 /*
4212 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4213 * reach the end of packet and since we can't make sure that we have
4214 * incoming data, we must reset the BMU while it is not during a DMA
4215 * transfer. Since it is possible that the Rx path is still active,
4216 * the Rx RAM buffer will be stopped first, so any possible incoming
4217 * data will not trigger a DMA. After the RAM buffer is stopped, the
4218 * BMU is polled until any DMA in progress is ended and only then it
4219 * will be reset.
4220 */
4221
4222 /* Disable the RAM Buffer receive queue. */
4223 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4224 for (i = 0; i < MSK_TIMEOUT; i++) {
4225 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4226 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4227 break;
4228 DELAY(1);
4229 }
4230 if (i == MSK_TIMEOUT)
4231 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4232 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4233 BMU_RST_SET | BMU_FIFO_RST);
4234 /* Reset the Rx prefetch unit. */
4235 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4236 PREF_UNIT_RST_SET);
4237 /* Reset the RAM Buffer receive queue. */
4238 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4239 /* Reset Rx MAC FIFO. */
4240 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4241
4242 /* Free Rx and Tx mbufs still in the queues. */
4243 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4244 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4245 if (rxd->rx_m != NULL) {
4246 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4247 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4248 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4249 rxd->rx_dmamap);
4250 m_freem(rxd->rx_m);
4251 rxd->rx_m = NULL;
4252 }
4253 }
4254 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4255 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4256 if (jrxd->rx_m != NULL) {
4257 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4258 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4259 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4260 jrxd->rx_dmamap);
4261 m_freem(jrxd->rx_m);
4262 jrxd->rx_m = NULL;
4263 }
4264 }
4265 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4266 txd = &sc_if->msk_cdata.msk_txdesc[i];
4267 if (txd->tx_m != NULL) {
4268 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4269 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4270 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4271 txd->tx_dmamap);
4272 m_freem(txd->tx_m);
4273 txd->tx_m = NULL;
4274 }
4275 }
4276
4277 /*
4278 * Mark the interface down.
4279 */
4280 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4281 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4282 }
4283
4284 /*
4285 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
4286 * counter clears high 16 bits of the counter such that accessing
4287 * lower 16 bits should be the last operation.
4288 */
4289 #define MSK_READ_MIB32(x, y) \
4290 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
4291 (uint32_t)GMAC_READ_2(sc, x, y))
4292 #define MSK_READ_MIB64(x, y) \
4293 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
4294 (uint64_t)MSK_READ_MIB32(x, y))
4295
4296 static void
msk_stats_clear(struct msk_if_softc * sc_if)4297 msk_stats_clear(struct msk_if_softc *sc_if)
4298 {
4299 struct msk_softc *sc;
4300 uint16_t gmac;
4301 int i;
4302
4303 MSK_IF_LOCK_ASSERT(sc_if);
4304
4305 sc = sc_if->msk_softc;
4306 /* Set MIB Clear Counter Mode. */
4307 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4308 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4309 /* Read all MIB Counters with Clear Mode set. */
4310 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
4311 (void)MSK_READ_MIB32(sc_if->msk_port, i);
4312 /* Clear MIB Clear Counter Mode. */
4313 gmac &= ~GM_PAR_MIB_CLR;
4314 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4315 }
4316
4317 static void
msk_stats_update(struct msk_if_softc * sc_if)4318 msk_stats_update(struct msk_if_softc *sc_if)
4319 {
4320 struct msk_softc *sc;
4321 if_t ifp;
4322 struct msk_hw_stats *stats;
4323 uint16_t gmac;
4324
4325 MSK_IF_LOCK_ASSERT(sc_if);
4326
4327 ifp = sc_if->msk_ifp;
4328 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
4329 return;
4330 sc = sc_if->msk_softc;
4331 stats = &sc_if->msk_stats;
4332 /* Set MIB Clear Counter Mode. */
4333 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4334 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4335
4336 /* Rx stats. */
4337 stats->rx_ucast_frames +=
4338 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4339 stats->rx_bcast_frames +=
4340 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4341 stats->rx_pause_frames +=
4342 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4343 stats->rx_mcast_frames +=
4344 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4345 stats->rx_crc_errs +=
4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4347 stats->rx_good_octets +=
4348 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4349 stats->rx_bad_octets +=
4350 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4351 stats->rx_runts +=
4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4353 stats->rx_runt_errs +=
4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4355 stats->rx_pkts_64 +=
4356 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4357 stats->rx_pkts_65_127 +=
4358 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4359 stats->rx_pkts_128_255 +=
4360 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4361 stats->rx_pkts_256_511 +=
4362 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4363 stats->rx_pkts_512_1023 +=
4364 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4365 stats->rx_pkts_1024_1518 +=
4366 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4367 stats->rx_pkts_1519_max +=
4368 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4369 stats->rx_pkts_too_long +=
4370 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4371 stats->rx_pkts_jabbers +=
4372 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4373 stats->rx_fifo_oflows +=
4374 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4375
4376 /* Tx stats. */
4377 stats->tx_ucast_frames +=
4378 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4379 stats->tx_bcast_frames +=
4380 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4381 stats->tx_pause_frames +=
4382 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4383 stats->tx_mcast_frames +=
4384 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4385 stats->tx_octets +=
4386 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4387 stats->tx_pkts_64 +=
4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4389 stats->tx_pkts_65_127 +=
4390 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4391 stats->tx_pkts_128_255 +=
4392 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4393 stats->tx_pkts_256_511 +=
4394 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4395 stats->tx_pkts_512_1023 +=
4396 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4397 stats->tx_pkts_1024_1518 +=
4398 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4399 stats->tx_pkts_1519_max +=
4400 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4401 stats->tx_colls +=
4402 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4403 stats->tx_late_colls +=
4404 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4405 stats->tx_excess_colls +=
4406 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4407 stats->tx_multi_colls +=
4408 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4409 stats->tx_single_colls +=
4410 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4411 stats->tx_underflows +=
4412 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4413 /* Clear MIB Clear Counter Mode. */
4414 gmac &= ~GM_PAR_MIB_CLR;
4415 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4416 }
4417
4418 static int
msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)4419 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4420 {
4421 struct msk_softc *sc;
4422 struct msk_if_softc *sc_if;
4423 uint32_t result, *stat;
4424 int off;
4425
4426 sc_if = (struct msk_if_softc *)arg1;
4427 sc = sc_if->msk_softc;
4428 off = arg2;
4429 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4430
4431 MSK_IF_LOCK(sc_if);
4432 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4433 result += *stat;
4434 MSK_IF_UNLOCK(sc_if);
4435
4436 return (sysctl_handle_int(oidp, &result, 0, req));
4437 }
4438
4439 static int
msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)4440 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4441 {
4442 struct msk_softc *sc;
4443 struct msk_if_softc *sc_if;
4444 uint64_t result, *stat;
4445 int off;
4446
4447 sc_if = (struct msk_if_softc *)arg1;
4448 sc = sc_if->msk_softc;
4449 off = arg2;
4450 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4451
4452 MSK_IF_LOCK(sc_if);
4453 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4454 result += *stat;
4455 MSK_IF_UNLOCK(sc_if);
4456
4457 return (sysctl_handle_64(oidp, &result, 0, req));
4458 }
4459
4460 #undef MSK_READ_MIB32
4461 #undef MSK_READ_MIB64
4462
4463 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
4464 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4465 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4466 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
4467 "IU", d)
4468 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
4469 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \
4470 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \
4471 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
4472 "QU", d)
4473
4474 static void
msk_sysctl_node(struct msk_if_softc * sc_if)4475 msk_sysctl_node(struct msk_if_softc *sc_if)
4476 {
4477 struct sysctl_ctx_list *ctx;
4478 struct sysctl_oid_list *child, *schild;
4479 struct sysctl_oid *tree;
4480
4481 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4482 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4483
4484 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4485 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics");
4486 schild = SYSCTL_CHILDREN(tree);
4487 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
4488 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics");
4489 child = SYSCTL_CHILDREN(tree);
4490 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4491 child, rx_ucast_frames, "Good unicast frames");
4492 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4493 child, rx_bcast_frames, "Good broadcast frames");
4494 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4495 child, rx_pause_frames, "Pause frames");
4496 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4497 child, rx_mcast_frames, "Multicast frames");
4498 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4499 child, rx_crc_errs, "CRC errors");
4500 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4501 child, rx_good_octets, "Good octets");
4502 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4503 child, rx_bad_octets, "Bad octets");
4504 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4505 child, rx_pkts_64, "64 bytes frames");
4506 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4507 child, rx_pkts_65_127, "65 to 127 bytes frames");
4508 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4509 child, rx_pkts_128_255, "128 to 255 bytes frames");
4510 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4511 child, rx_pkts_256_511, "256 to 511 bytes frames");
4512 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4513 child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4514 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4515 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4516 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4517 child, rx_pkts_1519_max, "1519 to max frames");
4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4519 child, rx_pkts_too_long, "frames too long");
4520 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4521 child, rx_pkts_jabbers, "Jabber errors");
4522 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
4523 child, rx_fifo_oflows, "FIFO overflows");
4524
4525 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
4526 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics");
4527 child = SYSCTL_CHILDREN(tree);
4528 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4529 child, tx_ucast_frames, "Unicast frames");
4530 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4531 child, tx_bcast_frames, "Broadcast frames");
4532 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4533 child, tx_pause_frames, "Pause frames");
4534 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4535 child, tx_mcast_frames, "Multicast frames");
4536 MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4537 child, tx_octets, "Octets");
4538 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4539 child, tx_pkts_64, "64 bytes frames");
4540 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4541 child, tx_pkts_65_127, "65 to 127 bytes frames");
4542 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4543 child, tx_pkts_128_255, "128 to 255 bytes frames");
4544 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4545 child, tx_pkts_256_511, "256 to 511 bytes frames");
4546 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4547 child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4548 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4549 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4550 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4551 child, tx_pkts_1519_max, "1519 to max frames");
4552 MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4553 child, tx_colls, "Collisions");
4554 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4555 child, tx_late_colls, "Late collisions");
4556 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4557 child, tx_excess_colls, "Excessive collisions");
4558 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4559 child, tx_multi_colls, "Multiple collisions");
4560 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4561 child, tx_single_colls, "Single collisions");
4562 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4563 child, tx_underflows, "FIFO underflows");
4564 }
4565
4566 #undef MSK_SYSCTL_STAT32
4567 #undef MSK_SYSCTL_STAT64
4568
4569 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)4570 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4571 {
4572 int error, value;
4573
4574 if (!arg1)
4575 return (EINVAL);
4576 value = *(int *)arg1;
4577 error = sysctl_handle_int(oidp, &value, 0, req);
4578 if (error || !req->newptr)
4579 return (error);
4580 if (value < low || value > high)
4581 return (EINVAL);
4582 *(int *)arg1 = value;
4583
4584 return (0);
4585 }
4586
4587 static int
sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)4588 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4589 {
4590
4591 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4592 MSK_PROC_MAX));
4593 }
4594