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Searched refs:getReg (Results 1 – 25 of 584) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
436 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
471 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
507 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
545 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
576 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
111 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
113 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
121 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
123 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
149 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
150 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
158 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
159 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
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H A DSystemZShortenInst.cpp78 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
184 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
185 SystemZMC::getFirstReg(LHSMO.getReg()) < 16 && in shortenFusedFPOp()
186 SystemZMC::getFirstReg(RHSMO.getReg()) < 16 && in shortenFusedFPOp()
187 SystemZMC::getFirstReg(AccMO.getReg()) < 16 && in shortenFusedFPOp()
188 DstMO.getReg() == AccMO.getReg()) { in shortenFusedFPOp()
359 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) && in processBlock()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp54 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
221 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
281 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
324 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
449 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
502 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
508 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
591 MRI.getType(Src.getReg()).isValid()) { in computeNumSignBits()
599 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
607 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
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H A DCombinerHelper.cpp188 Register Reg = MO.getReg(); in matchCombineConcatVectors()
683 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
1032 {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()}); in applyCombineDivRem()
1452 .getReg(0); in optimizeMemcpy()
2298 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge()
2679 return MOP1.getReg() == MOP2.getReg(); in matchEqualDefs()
2766 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), in matchSelectSameVal()
2772 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), in matchBinOpSameVal()
2778 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(OpIdx).getReg(), in matchOperandIsZero()
3299 replaceRegWith(MRI, MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applyNotCmp()
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H A DLegalizerHelper.cpp1236 .getReg(0); in narrowScalar()
1253 .getReg(0)); in narrowScalar()
1261 .getReg(0)); in narrowScalar()
1342 MO.setReg(ExtB.getReg(0)); in widenScalarSrc()
1349 MO.setReg(ExtB.getReg(0)); in narrowScalarSrc()
1397 MO.setReg(Concat.getReg(0)); in moreElementsVectorSrc()
1854 .getReg(0); in widenScalarAddSubOverflow()
3468 .getReg(0); in clampDynamicVectorIndex()
4665 .getReg(0); in fewerElementsVectorReductions()
5102 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); in multiplyRegisters()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp388 Register Def = Copy.getOperand(0).getReg(); in isBackwardPropagatableRegClassCopy()
457 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
499 if (!MOUse.getReg()) in forwardUses()
515 Register CopySrcReg = CopySrc.getReg(); in forwardUses()
518 if (MOUse.getReg() != CopyDstReg) { in forwardUses()
673 Register Reg = MO.getReg(); in ForwardCopyPropagateBlock()
757 Register Def = MI.getOperand(0).getReg(); in isBackwardPropagatableCopy()
758 Register Src = MI.getOperand(1).getReg(); in isBackwardPropagatableCopy()
784 if (!MODef.getReg()) in propagateDefs()
799 if (MODef.getReg() != Src) in propagateDefs()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp160 Register Reg = Op.getReg(); in applyBank()
827 Register OldReg = Op.getReg(); in executeInWaterfallLoop()
839 Register OpReg = Op.getReg(); in executeInWaterfallLoop()
936 .getReg(0); in executeInWaterfallLoop()
987 Op.setReg(Merge.getReg(0)); in executeInWaterfallLoop()
990 Op.setReg(Merge.getReg(0)); in executeInWaterfallLoop()
1326 return Def->getOperand(0).getReg(); in getSrcRegIgnoringCopies()
1668 return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1674 return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1678 return std::make_pair(Bitcast.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
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H A DAMDGPULegalizerInfo.cpp2956 return {ResultLo.getReg(0), ResultHi.getReg(0)}; in emitReciprocalU64()
3294 .addUse(RDst.getReg(0)) in legalizeFDIV16()
3469 .addUse(Mul.getReg(0)) in legalizeFDIV64()
3738 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
3743 .getReg(0); in handleD16VData()
3753 .getReg(0); in handleD16VData()
3774 .getReg(0); in handleD16VData()
4002 Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0)); in legalizeBufferLoad()
4805 B.buildMerge(R1, {UnmergeRayDir.getReg(0), UnmergeRayDir.getReg(1)}); in legalizeBVHIntrinsic()
4806 B.buildMerge(R2, {UnmergeRayDir.getReg(2), UnmergeRayInvDir.getReg(0)}); in legalizeBVHIntrinsic()
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H A DSIShrinkInstructions.cpp71 Register Reg = Src0.getReg(); in foldImmediates()
365 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
366 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
370 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
484 Register X = Xop.getReg(); in matchSwap()
667 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
668 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
672 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { in runOnMachineFunction()
766 Register SReg = Src2->getReg(); in runOnMachineFunction()
786 if (SDst->getReg() != VCCReg) { in runOnMachineFunction()
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H A DSIFixSGPRCopies.cpp144 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses()
145 Register SrcReg = Copy.getOperand(1).getReg(); in getCopyRegClasses()
180 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy()
181 Register SrcReg = Src.getReg(); in tryChangeVGPRtoSGPRinCopy()
222 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence()
265 Register SrcReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
725 Src0.getReg() != AMDGPU::M0) && in runOnMachineFunction()
727 Src1.getReg() != AMDGPU::M0)) { in runOnMachineFunction()
735 if (MO->getReg().isVirtual()) { in runOnMachineFunction()
740 MO->getReg() == Def.getReg() && in runOnMachineFunction()
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H A DAMDGPUGlobalISelUtils.cpp36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset))) in getBaseWithConstantOffset()
37 return std::make_pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset)))) in getBaseWithConstantOffset()
41 return std::make_pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
47 if (mi_match(Def->getOperand(1).getReg(), MRI, in getBaseWithConstantOffset()
51 return std::make_pair(Base->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
54 return std::make_pair(Base->getOperand(0).getReg(), Offset); in getBaseWithConstantOffset()
H A DSIFoldOperands.cpp556 Register UseReg = OpToFold.getReg(); in tryToFoldACImm()
744 Register UseReg = OpToFold.getReg(); in foldOperand()
917 Register UseReg = UseOp.getReg(); in foldOperand()
1342 Src0->getReg() != Src1->getReg() || in isClamp()
1389 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); in tryFoldClamp()
1489 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() && in isOMod()
1527 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); in tryFoldOMod()
1536 auto Reg = MI.getOperand(0).getReg(); in tryFoldRegSequence()
1550 if (TRI->isAGPR(*MRI, Op->getReg())) in tryFoldRegSequence()
1563 Reg = UseMI->getOperand(0).getReg(); in tryFoldRegSequence()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp257 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
258 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
278 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
279 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
294 Register V1 = MI.getOperand(1).getReg(); in matchZip()
715 .getReg(0); in applyDupLane()
877 .getReg(0); in getVectorFCMP()
884 .getReg(0); in getVectorFCMP()
891 .getReg(0); in getVectorFCMP()
898 .getReg(0); in getVectorFCMP()
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H A DAArch64InstructionSelector.cpp622 return RegSequence.getReg(0); in createTuple()
1534 emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, in selectCompareBranchFedByFCmp()
2076 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()}); in earlySelectSHL()
3153 .getReg(0); in select()
3252 if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB, in select()
3357 .getReg(0); in selectReduction()
4622 emitSelect(I.getOperand(0).getReg(), I.getOperand(2).getReg(), in tryOptSelect()
4750 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()}); in selectShuffleVector()
5050 {I.getOperand(0).getReg(), I.getOperand(1).getReg()}, in selectIntrinsicWithSideEffects()
5978 return Copy.getReg(0); in moveScalarRegClass()
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H A DAArch64RegisterBankInfo.cpp443 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
616 Register DstReg = MI.getOperand(0).getReg(); in getInstrMapping()
617 Register SrcReg = MI.getOperand(1).getReg(); in getInstrMapping()
669 if (!MO.isReg() || !MO.getReg()) in getInstrMapping()
672 LLT Ty = MRI.getType(MO.getReg()); in getInstrMapping()
689 Register ScalarReg = MI.getOperand(1).getReg(); in getInstrMapping()
713 Register SrcReg = MI.getOperand(1).getReg(); in getInstrMapping()
772 Register VReg = MI.getOperand(0).getReg(); in getInstrMapping()
823 Register VReg = MI.getOperand(Idx).getReg(); in getInstrMapping()
879 auto Src = MI.getOperand(1).getReg(); in getInstrMapping()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp111 printRegName(O, Dst.getReg()); in printInst()
113 printRegName(O, MO1.getReg()); in printInst()
116 printRegName(O, MO2.getReg()); in printInst()
316 unsigned Reg = Op.getReg(); in printOperand()
403 printRegName(O, MO1.getReg()); in printSORegRegOperand()
443 if (!MO2.getReg()) { in printAM2PreOrOffsetIndexOp()
512 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
541 if (MO2.getReg()) { in printAM3PreOrOffsetIndexOp()
582 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
728 if (MO.getReg() == 0) in printAddrMode6OffsetOperand()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp239 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
284 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
297 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
304 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
364 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
378 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
380 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
402 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
424 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
439 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h59 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
108 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
167 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
530 if (Def.getReg() == SearchDef) in getDefIndex()
627 return BV.getReg(StartSrcIdx); in findValueFromBuildVector()
721 if (MO.getReg() == DefReg) in findValueFromDef()
759 LLT DestTy = MRI.getType(MI.getReg(0)); in tryCombineUnmergeValues()
769 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues()
825 Register Def = MI.getReg(I); in tryCombineUnmergeValues()
931 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp160 Register Reg = Op->getReg(); in getVRegDefOrNull()
547 MI.getOperand(0).getReg()) in simplifyCode()
577 MI.getOperand(0).getReg()) in simplifyCode()
655 MI.getOperand(0).getReg()) in simplifyCode()
842 MI.getOperand(0).getReg()) in simplifyCode()
889 MI.getOperand(0).getReg()) in simplifyCode()
942 Register DominatorReg = Op2.getReg(); in simplifyCode()
979 MI.getOperand(0).getReg()) in simplifyCode()
1099 return Phi->getOperand(I-1).getReg(); in getIncomingRegForBlock()
1120 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
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H A DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
501 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
537 Register R = MD.getReg(); in collectIndRegsForLoop()
602 Register R = Op.getReg(); in createHalfInstr()
676 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
810 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
946 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
960 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
1079 Register R = Op.getReg(); in replaceSubregUses()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp82 if (MO.isReg() && MO.getReg().isValid() && in runOnMachineFunction()
83 MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
90 if (MO.getReg() == Elem.Reg) { in runOnMachineFunction()
92 LLVM_DEBUG(dbgs() << "Debug Value VReg " << MO.getReg() in runOnMachineFunction()
109 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
112 assert(Prev.Reg == MO.getReg() && in runOnMachineFunction()
130 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
131 Stack.push_back({MO.getReg(), nullptr}); in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp194 Register OrigDestReg = OrigMI->getOperand(0).getReg(); in getSuperRegDestIfDead()
276 TRI->regsOverlap(SuperDestReg, MO.getReg())) in getSuperRegDestIfDead()
311 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceLoad()
312 MI->getOperand(0).getReg()); in tryReplaceLoad()
329 Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32); in tryReplaceCopy()
334 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
335 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
346 .addReg(OldSrc.getReg(), RegState::Implicit); in tryReplaceCopy()
350 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
366 MI->getOperand(0).getReg() == X86::AX && in tryReplaceExtend()
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