1480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
2480093f4SDimitry Andric //
3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6480093f4SDimitry Andric //
7480093f4SDimitry Andric //===----------------------------------------------------------------------===//
8480093f4SDimitry Andric
9480093f4SDimitry Andric #include "AMDGPUGlobalISelUtils.h"
10480093f4SDimitry Andric #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
11480093f4SDimitry Andric #include "llvm/IR/Constants.h"
12480093f4SDimitry Andric
13480093f4SDimitry Andric using namespace llvm;
14480093f4SDimitry Andric using namespace MIPatternMatch;
15480093f4SDimitry Andric
16af732203SDimitry Andric std::pair<Register, unsigned>
getBaseWithConstantOffset(MachineRegisterInfo & MRI,Register Reg)17480093f4SDimitry Andric AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
18480093f4SDimitry Andric MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
19480093f4SDimitry Andric if (!Def)
20af732203SDimitry Andric return std::make_pair(Reg, 0);
21480093f4SDimitry Andric
22480093f4SDimitry Andric if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
23480093f4SDimitry Andric unsigned Offset;
24480093f4SDimitry Andric const MachineOperand &Op = Def->getOperand(1);
25480093f4SDimitry Andric if (Op.isImm())
26480093f4SDimitry Andric Offset = Op.getImm();
27480093f4SDimitry Andric else
28480093f4SDimitry Andric Offset = Op.getCImm()->getZExtValue();
29480093f4SDimitry Andric
30af732203SDimitry Andric return std::make_pair(Register(), Offset);
31480093f4SDimitry Andric }
32480093f4SDimitry Andric
33480093f4SDimitry Andric int64_t Offset;
34480093f4SDimitry Andric if (Def->getOpcode() == TargetOpcode::G_ADD) {
35480093f4SDimitry Andric // TODO: Handle G_OR used for add case
36480093f4SDimitry Andric if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37af732203SDimitry Andric return std::make_pair(Def->getOperand(1).getReg(), Offset);
38480093f4SDimitry Andric
39480093f4SDimitry Andric // FIXME: matcher should ignore copies
40480093f4SDimitry Andric if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41af732203SDimitry Andric return std::make_pair(Def->getOperand(1).getReg(), Offset);
42480093f4SDimitry Andric }
43480093f4SDimitry Andric
44*5f7ddb14SDimitry Andric // Handle G_PTRTOINT (G_PTR_ADD base, const) case
45*5f7ddb14SDimitry Andric if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
46*5f7ddb14SDimitry Andric MachineInstr *Base;
47*5f7ddb14SDimitry Andric if (mi_match(Def->getOperand(1).getReg(), MRI,
48*5f7ddb14SDimitry Andric m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
49*5f7ddb14SDimitry Andric // If Base was int converted to pointer, simply return int and offset.
50*5f7ddb14SDimitry Andric if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
51*5f7ddb14SDimitry Andric return std::make_pair(Base->getOperand(1).getReg(), Offset);
52*5f7ddb14SDimitry Andric
53*5f7ddb14SDimitry Andric // Register returned here will be of pointer type.
54*5f7ddb14SDimitry Andric return std::make_pair(Base->getOperand(0).getReg(), Offset);
55*5f7ddb14SDimitry Andric }
56*5f7ddb14SDimitry Andric }
57*5f7ddb14SDimitry Andric
58af732203SDimitry Andric return std::make_pair(Reg, 0);
59480093f4SDimitry Andric }
605ffd83dbSDimitry Andric
isLegalVOP3PShuffleMask(ArrayRef<int> Mask)615ffd83dbSDimitry Andric bool AMDGPU::isLegalVOP3PShuffleMask(ArrayRef<int> Mask) {
625ffd83dbSDimitry Andric assert(Mask.size() == 2);
635ffd83dbSDimitry Andric
645ffd83dbSDimitry Andric // If one half is undef, the other is trivially in the same reg.
655ffd83dbSDimitry Andric if (Mask[0] == -1 || Mask[1] == -1)
665ffd83dbSDimitry Andric return true;
675ffd83dbSDimitry Andric return (Mask[0] & 2) == (Mask[1] & 2);
685ffd83dbSDimitry Andric }
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