Lines Matching refs:getReg
36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
111 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
113 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
120 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorStore()
121 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
123 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
149 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
150 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
158 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
159 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
167 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
176 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
185 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
186 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
194 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
195 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
203 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
212 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
233 .addReg(MI->getOperand(0).getReg())); in emitInstruction()
248 .addReg(MI->getOperand(0).getReg()); in emitInstruction()
265 .addReg(MI->getOperand(0).getReg()); in emitInstruction()
272 .addReg(MI->getOperand(2).getReg()); in emitInstruction()
277 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
278 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
280 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
286 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
287 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
289 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
295 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
298 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
304 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
307 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
313 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
314 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
316 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
322 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
323 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
325 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
331 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
334 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
340 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
343 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
363 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
369 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in emitInstruction()
375 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in emitInstruction()
391 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
392 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg())) in emitInstruction()
393 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); in emitInstruction()
399 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
400 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())); in emitInstruction()
441 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg())) in emitInstruction()
442 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())) in emitInstruction()
448 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
449 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
450 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
546 Register LenMinus1Reg = MI->getOperand(1).getReg(); in emitInstruction()
547 Register DestReg = MI->getOperand(2).getReg(); in emitInstruction()
549 Register SrcReg = MI->getOperand(4).getReg(); in emitInstruction()
686 ScratchReg = MI.getOperand(ScratchIdx).getReg(); in LowerPATCHPOINT()
772 SystemZ::GR128BitRegClass.contains(MO.getReg())) in PrintAsmOperand()
774 MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); in PrintAsmOperand()
789 SystemZInstPrinter::printAddress(MAI, MI->getOperand(OpNo).getReg(), in PrintAsmMemoryOperand()
791 MI->getOperand(OpNo + 2).getReg(), OS); in PrintAsmMemoryOperand()