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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
53 def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">,
186 …def UseMovtInPic : Predicate<"Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt(…
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H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
142 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
164 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
173 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
192 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
203 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
221 if (NumMEMCPYs > 1 && Subtarget.hasMinSize()) { in EmitTargetCodeForMemcpy()
302 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemset() local
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H A DARMISelLowering.cpp474 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() && in ARMTargetLowering()
1130 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() in ARMTargetLowering()
1131 || (Subtarget->isThumb2() && !Subtarget->hasDSP())) in ARMTargetLowering()
1298 if (!Subtarget->isThumb() || !Subtarget->isMClass()) in ARMTargetLowering()
1562 if (Subtarget->isThumb() || Subtarget->isThumb2()) in ARMTargetLowering()
4959 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in LowerADDSUBSAT()
5310 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) in LowerSELECT_CC()
5720 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) { in LowerBR_JT()
12579 if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() && in AddCombineTo64bitMLAL()
12626 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in AddCombineTo64bitUMAAL()
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H A DARMFastISel.cpp110 const ARMSubtarget *Subtarget; member in __anon196e23e40111::ARMFastISel
125 Subtarget( in ARMFastISel()
490 if (Subtarget->useMovt()) in ARMMaterializeInt()
528 if (Subtarget->isROPI() || Subtarget->isRWPI()) in ARMMaterializeGV()
544 if (Subtarget->useMovt() && in ARMMaterializeGV()
604 if ((Subtarget->isTargetELF() && Subtarget->isGVInGOT(GV)) || in ARMMaterializeGV()
1344 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64())) in ARMEmitCmp()
1485 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false; in SelectFPExt()
1504 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false; in SelectFPTrunc()
1789 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64())) in SelectBinaryFPOp()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
130 if (Subtarget.isABI_N64()) in getCallPreservedMask()
133 if (Subtarget.isABI_N32()) in getCallPreservedMask()
136 if (Subtarget.isFP64bit()) in getCallPreservedMask()
139 if (Subtarget.isFPXX()) in getCallPreservedMask()
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H A DMipsISelLowering.cpp478 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) in MipsTargetLowering()
1060 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performSUBCombine()
1075 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && in performADDCombine()
2021 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); in lowerBRCOND()
2630 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { in lowerShiftRightParts()
4579 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoSELECT()
4656 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && in emitPseudoD_SELECT()
4766 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_W()
4812 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitLDR_D()
4896 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { in emitSTR_W()
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H A DMipsAsmPrinter.cpp82 if (Subtarget->inMips16Mode()) in runOnMachineFunction()
96 if (Subtarget->isTargetNaCl()) in runOnMachineFunction()
121 if (Subtarget->hasMips64r6()) { in emitPseudoIndirectBranch()
406 if (Subtarget->isTargetNaCl()) in emitFunctionEntryLabel()
412 TS.updateABIInfo(*Subtarget); in emitFunctionEntryLabel()
416 if (Subtarget->inMips16Mode()) in emitFunctionEntryLabel()
439 if (!Subtarget->inMips16Mode()) { in emitFunctionBodyStart()
454 if (!Subtarget->inMips16Mode()) { in emitFunctionBodyEnd()
643 if (Subtarget->isLittle()) in PrintAsmMemoryOperand()
647 if (!Subtarget->isLittle()) in PrintAsmMemoryOperand()
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H A DMipsSEISelLowering.cpp70 if (Subtarget.isGP64bit()) in MipsSETargetLowering()
73 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { in MipsSETargetLowering()
85 if (Subtarget.hasDSP()) { in MipsSETargetLowering()
114 if (Subtarget.hasDSPR2()) in MipsSETargetLowering()
117 if (Subtarget.hasMSA()) { in MipsSETargetLowering()
188 if (Subtarget.hasCnMips()) in MipsSETargetLowering()
217 if (Subtarget.hasMips32r2() && !Subtarget.useSoftFloat() && in MipsSETargetLowering()
485 if (!Subtarget.hasMSA()) in performANDCombine()
600 if (!Subtarget.hasMSA()) in performORCombine()
3656 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); in emitFPROUND_PSEUDO()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp52 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
75 if (!Subtarget) in getCPUSuffix()
78 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
80 if (Subtarget->hasP9Vector()) in getCPUSuffix()
82 if (Subtarget->hasP8Vector()) in getCPUSuffix()
84 if (Subtarget->isAIXABI()) in getCPUSuffix()
97 StringRef Suffix = getCPUSuffix(Subtarget); in createMASSVFuncName()
144 std::string MASSVEntryName = createMASSVFuncName(Func, Subtarget); in lowerMASSVCall()
161 const PPCSubtarget *Subtarget; in runOnModule() local
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H A DPPCRegisterInfo.cpp168 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
193 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
219 if (Subtarget.isAIXABI()) { in getCalleeSavedRegs()
225 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
227 else if (Subtarget.hasSPE()) in getCalleeSavedRegs()
237 if (Subtarget.hasVSX()) { in getCallPreservedMask()
250 if (Subtarget.isAIXABI()) { in getCallPreservedMask()
331 if (Subtarget.isAIXABI()) in getReservedRegs()
358 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && in getReservedRegs()
458 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI()) in isCallerPreservedPhysReg()
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H A DPPCFrameLowering.cpp84 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
230 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
235 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
242 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
541 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in twoUniqueScratchRegsRequired()
570 if (!Subtarget.isELFv2ABI() || !Subtarget.isPPC64()) in stackUpdateCanBeMoved()
620 bool isPPC64 = Subtarget.isPPC64(); in emitPrologue()
1233 bool isPPC64 = Subtarget.isPPC64(); in inlineStackProbe()
1264 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in inlineStackProbe()
1566 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in emitEpilogue()
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H A DPPCISelLowering.cpp430 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
651 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
3124 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3131 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3148 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3738 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
8182 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8473 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8621 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9174 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td27 // Subtarget Features (device properties)
643 // Subtarget Features (options and debugging)
1251 Predicate<"!Subtarget->hasGFX90AInsts() &&"
1279 Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1283 Predicate<"Subtarget->hasGFX90AInsts()">,
1287 Predicate<"!Subtarget->hasGFX90AInsts()">,
1291 Predicate<"!Subtarget->hasGFX90AInsts() &&"
1297 Predicate<"Subtarget->hasGFX90AInsts()">,
1301 Predicate<"Subtarget->hasMAIInsts()">,
1374 Predicate<"Subtarget->hasSDWA()">,
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCV.td18 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
25 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
32 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
40 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
55 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
133 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
158 def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
172 def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
194 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
197 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
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H A DRISCVISelLowering.cpp49 if (Subtarget.isRV32E()) in RISCVTargetLowering()
88 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
90 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
240 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in RISCVTargetLowering()
348 if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) in RISCVTargetLowering()
398 if (Subtarget.is64Bit()) in RISCVTargetLowering()
1021 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getRegisterTypeForCallingConv()
1032 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getNumRegistersForCallingConv()
5016 Subtarget.is64Bit() && Subtarget.hasStdExtM() && in ReplaceNodeResults()
6458 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in targetShrinkDemandedConstant()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
154 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
188 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
210 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
215 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
227 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
247 if (Subtarget.hasERMSB()) in emitConstantSizeRepmov()
250 assert(!Subtarget.hasERMSB() && "No efficient RepMovs"); in emitConstantSizeRepmov()
261 emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitConstantSizeRepmov()
306 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
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H A DX86ISelLowering.cpp145 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
364 if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) { in X86TargetLowering()
497 if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow()) in X86TargetLowering()
729 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
1095 !(Subtarget.hasBWI() && Subtarget.hasVLX())) in X86TargetLowering()
2319 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
8250 if (Subtarget.hasSSE3() && !Subtarget.hasXOP() && in LowerBuildVectorv4x32()
10093 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
10128 if (Subtarget.hasVLX() && Subtarget.hasVBMI()) in createVariablePermute()
10162 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
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H A DX86RegisterInfo.cpp130 if (!Subtarget.hasAVX512() && in getLargestLegalSuperClass()
137 if (!Subtarget.hasVLX() && in getLargestLegalSuperClass()
144 if (Subtarget.hasVLX() && in getLargestLegalSuperClass()
151 if (Subtarget.hasAVX512() && in getLargestLegalSuperClass()
181 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
197 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
202 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
281 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
282 bool HasAVX = Subtarget.hasAVX(); in getCalleeSavedRegs()
417 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
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H A DX86LoadValueInjectionRetHardening.cpp63 const X86Subtarget *Subtarget = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
64 if (!Subtarget->useLVIControlFlowIntegrity() || !Subtarget->is64Bit()) in runOnMachineFunction()
73 const X86RegisterInfo *TRI = Subtarget->getRegisterInfo(); in runOnMachineFunction()
74 const X86InstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DX86FastISel.cpp50 const X86Subtarget *Subtarget; member in __anon2295b5b00111::X86FastISel
1939 if (!Subtarget->is64Bit()) in X86SelectDivRem()
2035 if (!Subtarget->hasCMov()) in X86FastEmitCMoveSelect()
2206 if (Subtarget->hasAVX512()) { in X86FastEmitSSESelect()
2597 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) in fastLowerIntrinsicCall()
2798 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2979 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2985 if (!Subtarget->hasSSE2()) in fastLowerIntrinsicCall()
3058 if (!Subtarget->is64Bit()) in fastLowerArguments()
3144 if (Subtarget->is64Bit()) in computeBytesPoppedByCalleeForSRet()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
67 if (!Subtarget.is64Bit()) in getReservedRegs()
82 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
90 if (!Subtarget.isV9()) { in getReservedRegs()
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
182 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
196 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
H A DLeonPasses.cpp40 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
41 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
77 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
127 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
128 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyUtilities.cpp101 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFunctionTableSymbol() argument
114 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFunctionTableSymbol()
120 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFuncrefCallTableSymbol() argument
139 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFuncrefCallTableSymbol()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
198 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
202 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
220 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
224 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
239 const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs()
249 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
258 const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>(); in getReservedRegs() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp95 const AArch64Subtarget &Subtarget; member
107 Subtarget(Subtarget_), IsReturn(IsReturn) {} in AArch64OutgoingValueAssigner()
326 const AArch64Subtarget &Subtarget; member
556 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); in lowerFormalArguments() local
557 if (!Subtarget.isTargetDarwin()) { in lowerFormalArguments()
591 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>(); in lowerFormalArguments() local
592 if (Subtarget.hasCustomCallingConv()) in lowerFormalArguments()
593 Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF); in lowerFormalArguments()
916 auto TRI = Subtarget.getRegisterInfo(); in lowerTailCall()
918 if (Subtarget.hasCustomCallingConv()) in lowerTailCall()
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