Lines Matching refs:Subtarget
456 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
457 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
458 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
463 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() && in ARMTargetLowering()
464 !Subtarget->isTargetWatchOS()) { in ARMTargetLowering()
472 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
474 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() && in ARMTargetLowering()
475 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
549 if (Subtarget->isAAPCS_ABI() && in ARMTargetLowering()
550 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || in ARMTargetLowering()
551 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) { in ARMTargetLowering()
671 if (Subtarget->isTargetWindows()) { in ARMTargetLowering()
694 if (Subtarget->isTargetMachO() && in ARMTargetLowering()
695 !(Subtarget->isTargetIOS() && in ARMTargetLowering()
696 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) { in ARMTargetLowering()
704 if (!Subtarget->isTargetWatchABI()) { in ARMTargetLowering()
705 if (Subtarget->isAAPCS_ABI()) { in ARMTargetLowering()
718 if (Subtarget->isTargetAEABI()) { in ARMTargetLowering()
735 if (Subtarget->isThumb1Only()) in ARMTargetLowering()
740 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() && in ARMTargetLowering()
741 Subtarget->hasFPRegs()) { in ARMTargetLowering()
744 if (!Subtarget->hasVFP2Base()) in ARMTargetLowering()
746 if (!Subtarget->hasFP64()) in ARMTargetLowering()
750 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
759 if (Subtarget->hasBF16()) { in ARMTargetLowering()
762 if (!Subtarget->hasFullFP16()) in ARMTargetLowering()
784 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
785 addMVEVectorTypes(Subtarget->hasMVEFloatOps()); in ARMTargetLowering()
788 if (Subtarget->hasLOB()) { in ARMTargetLowering()
793 if (Subtarget->hasNEON()) { in ARMTargetLowering()
807 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
812 if (Subtarget->hasBF16()) { in ARMTargetLowering()
818 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) { in ARMTargetLowering()
856 if (Subtarget->hasNEON()) { in ARMTargetLowering()
957 if (!Subtarget->hasVFP4Base()) { in ARMTargetLowering()
981 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()
998 if (Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()
1008 if (!Subtarget->hasFP64()) { in ARMTargetLowering()
1051 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) { in ARMTargetLowering()
1054 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1060 if (!Subtarget->hasFP16()) { in ARMTargetLowering()
1065 computeRegisterProperties(Subtarget->getRegisterInfo()); in ARMTargetLowering()
1083 if (!Subtarget->isThumb1Only()) { in ARMTargetLowering()
1108 if (Subtarget->hasDSP()) { in ARMTargetLowering()
1118 if (Subtarget->hasBaseDSP()) { in ARMTargetLowering()
1126 if (Subtarget->isThumb1Only()) { in ARMTargetLowering()
1130 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() in ARMTargetLowering()
1131 || (Subtarget->isThumb2() && !Subtarget->hasDSP())) in ARMTargetLowering()
1146 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1150 if (Subtarget->isThumb1Only()) { in ARMTargetLowering()
1156 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) in ARMTargetLowering()
1167 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) { in ARMTargetLowering()
1176 if (Subtarget->hasPerfMon()) in ARMTargetLowering()
1180 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()
1183 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode() in ARMTargetLowering()
1184 : Subtarget->hasDivideInARMMode(); in ARMTargetLowering()
1191 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) { in ARMTargetLowering()
1203 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || in ARMTargetLowering()
1204 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || in ARMTargetLowering()
1205 Subtarget->isTargetWindows()) { in ARMTargetLowering()
1210 if (Subtarget->isTargetWindows()) { in ARMTargetLowering()
1263 if (Subtarget->getTargetTriple().isOSMSVCRT()) { in ARMTargetLowering()
1285 if (Subtarget->isTargetWindows()) in ARMTargetLowering()
1293 if (Subtarget->hasAnyDataBarrier() && in ARMTargetLowering()
1294 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) { in ARMTargetLowering()
1298 if (!Subtarget->isThumb() || !Subtarget->isMClass()) in ARMTargetLowering()
1303 if (!Subtarget->hasAcquireRelease() || in ARMTargetLowering()
1312 if (Subtarget->hasDataBarrier()) in ARMTargetLowering()
1316 Subtarget->hasAnyDataBarrier() ? Custom : Expand); in ARMTargetLowering()
1342 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()
1348 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() && in ARMTargetLowering()
1349 !Subtarget->isThumb1Only()) { in ARMTargetLowering()
1362 if (Subtarget->useSjLjEH()) in ARMTargetLowering()
1374 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1384 if (Subtarget->hasFullFP16()) in ARMTargetLowering()
1399 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() && in ARMTargetLowering()
1400 !Subtarget->isThumb1Only()) { in ARMTargetLowering()
1407 if (!Subtarget->hasVFP4Base()) { in ARMTargetLowering()
1413 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) { in ARMTargetLowering()
1415 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) { in ARMTargetLowering()
1421 if (!Subtarget->hasFP16()) { in ARMTargetLowering()
1443 if (Subtarget->hasFPARMv8Base()) { in ARMTargetLowering()
1452 if (Subtarget->hasNEON()) { in ARMTargetLowering()
1459 if (Subtarget->hasFP64()) { in ARMTargetLowering()
1472 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1489 if (Subtarget->hasNEON()) { in ARMTargetLowering()
1494 if (Subtarget->useNEONForSinglePrecisionFP()) { in ARMTargetLowering()
1505 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1527 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1530 if (Subtarget->hasV6Ops()) in ARMTargetLowering()
1532 if (Subtarget->isThumb1Only()) in ARMTargetLowering()
1537 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() || in ARMTargetLowering()
1538 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize()) in ARMTargetLowering()
1556 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder(); in ARMTargetLowering()
1558 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment())); in ARMTargetLowering()
1560 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4)); in ARMTargetLowering()
1562 if (Subtarget->isThumb() || Subtarget->isThumb2()) in ARMTargetLowering()
1567 return Subtarget->useSoftFloat(); in useSoftFloat()
1598 if (Subtarget->useNEONForSinglePrecisionFP()) in findRepresentativeClass()
1838 if ((Subtarget->hasMVEIntegerOps() && in getSetCCResultType()
1840 (Subtarget->hasMVEFloatOps() && (VT == MVT::v4f32 || VT == MVT::v8f16))) in getSetCCResultType()
1854 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in getRegClassFor()
1873 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()
1902 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in getSchedulingPreference()
2024 if (!Subtarget->isAAPCS_ABI()) in getEffectiveCallingConv()
2026 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && in getEffectiveCallingConv()
2034 if (!Subtarget->isAAPCS_ABI()) { in getEffectiveCallingConv()
2035 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg) in getEffectiveCallingConv()
2038 } else if (Subtarget->hasVFP2Base() && in getEffectiveCallingConv()
2039 !Subtarget->isThumb1Only() && !isVarArg) in getEffectiveCallingConv()
2085 if (Subtarget->hasFullFP16()) { in MoveToHPR()
2098 if (Subtarget->hasFullFP16()) { in MoveFromHPR()
2149 if (!Subtarget->isLittle()) in LowerCallResult()
2166 if (!Subtarget->isLittle()) in LowerCallResult()
2237 unsigned id = Subtarget->isLittle() ? 0 : 1; in PassF64ArgInRegs()
2294 if (!Subtarget->supportsTailCall()) in LowerCall()
2310 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() && in LowerCall()
2574 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO(); in LowerCall()
2576 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); in LowerCall()
2580 if (Subtarget->genLongCalls()) { in LowerCall()
2581 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) && in LowerCall()
2619 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking); in LowerCall()
2621 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { in LowerCall()
2622 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"); in LowerCall()
2631 } else if (Subtarget->isTargetCOFF()) { in LowerCall()
2632 assert(Subtarget->isTargetWindows() && in LowerCall()
2654 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { in LowerCall()
2692 if (Subtarget->isThumb()) { in LowerCall()
2695 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) in LowerCall()
2700 if (!isDirect && !Subtarget->hasV5TOps()) in LowerCall()
2702 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() && in LowerCall()
2704 !Subtarget->hasMinSize()) in LowerCall()
2738 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo(); in LowerCall()
2905 assert(Subtarget->supportsTailCall()); in IsEligibleForTailCallOptimization()
2910 if (Subtarget->isThumb1Only() && Outs.size() >= 4 && in IsEligibleForTailCallOptimization()
2955 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); in IsEligibleForTailCallOptimization()
2983 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in IsEligibleForTailCallOptimization()
3086 bool isLittleEndian = Subtarget->isLittle(); in LowerReturn()
3113 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) { in LowerReturn()
3207 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); in LowerReturn()
3233 !Subtarget->isMClass()) { in LowerReturn()
3234 if (Subtarget->isThumb1Only()) in LowerReturn()
3320 if (!Subtarget->supportsTailCall()) in mayBeEmittedAsTailCall()
3365 if (Subtarget->genExecuteOnly()) { in LowerConstantPool()
3403 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI(); in LowerBlockAddress()
3407 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; in LowerBlockAddress()
3451 assert(Subtarget->isTargetDarwin() && in LowerGlobalTLSAddressDarwin()
3495 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering"); in LowerGlobalTLSAddressWindows()
3554 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; in LowerToTLSGeneralDynamicModel()
3607 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; in LowerToTLSExecModels()
3648 if (Subtarget->isTargetDarwin()) in LowerGlobalTLSAddress()
3651 if (Subtarget->isTargetWindows()) in LowerGlobalTLSAddress()
3655 assert(Subtarget->isTargetELF() && "Only ELF implemented here"); in LowerGlobalTLSAddress()
3794 switch (Subtarget->getTargetTriple().getObjectFormat()) { in LowerGlobalAddress()
3814 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly()) in LowerGlobalAddressELF()
3828 } else if (Subtarget->isROPI() && IsRO) { in LowerGlobalAddressELF()
3833 } else if (Subtarget->isRWPI() && !IsRO) { in LowerGlobalAddressELF()
3836 if (Subtarget->useMovt()) { in LowerGlobalAddressELF()
3856 if (Subtarget->useMovt()) { in LowerGlobalAddressELF()
3873 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() && in LowerGlobalAddressDarwin()
3879 if (Subtarget->useMovt()) in LowerGlobalAddressDarwin()
3890 if (Subtarget->isGVIndirectSymbol(GV)) in LowerGlobalAddressDarwin()
3898 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported"); in LowerGlobalAddressWindows()
3899 assert(Subtarget->useMovt() && in LowerGlobalAddressWindows()
3901 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() && in LowerGlobalAddressWindows()
3952 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const { in LowerINTRINSIC_VOID()
3966 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo(); in LowerINTRINSIC_VOID()
3978 if (Subtarget->isThumb()) in LowerINTRINSIC_VOID()
3995 const ARMSubtarget *Subtarget) const { in LowerINTRINSIC_WO_CHAIN()
4054 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0; in LowerINTRINSIC_WO_CHAIN()
4133 const ARMSubtarget *Subtarget) { in LowerATOMIC_FENCE() argument
4140 if (!Subtarget->hasDataBarrier()) { in LowerATOMIC_FENCE()
4144 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && in LowerATOMIC_FENCE()
4153 if (Subtarget->isMClass()) { in LowerATOMIC_FENCE()
4156 } else if (Subtarget->preferISHSTBarriers() && in LowerATOMIC_FENCE()
4170 const ARMSubtarget *Subtarget) { in LowerPREFETCH() argument
4172 if (!(Subtarget->isThumb2() || in LowerPREFETCH()
4173 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) in LowerPREFETCH()
4180 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) in LowerPREFETCH()
4185 if (Subtarget->isThumb()) { in LowerPREFETCH()
4242 if (!Subtarget->isLittle()) in GetF64FormalArgument()
4690 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND && in getARMCmp()
4713 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL && in getARMCmp()
4766 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64); in getVFPCmp()
4957 const ARMSubtarget *Subtarget) { in LowerADDSUBSAT() argument
4959 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in LowerADDSUBSAT()
5132 if (!Subtarget->hasFP64() && VT == MVT::f64) { in getCMOV()
5297 return !Subtarget->hasVFP2Base(); in isUnsupportedFloatingType()
5299 return !Subtarget->hasFP64(); in isUnsupportedFloatingType()
5301 return !Subtarget->hasFullFP16(); in isUnsupportedFloatingType()
5310 if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) in LowerSELECT_CC()
5342 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal && in LowerSELECT_CC()
5365 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) { in LowerSELECT_CC()
5413 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 || in LowerSELECT_CC()
5440 if (Subtarget->hasFPARMv8Base() && in LowerSELECT_CC()
5474 const ARMSubtarget *Subtarget) { in canChangeToInt() argument
5482 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) in canChangeToInt()
5547 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget); in OptimizeVFPBrcond()
5549 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget); in OptimizeVFPBrcond()
5598 !Subtarget->isThumb1Only(); in LowerBRCOND()
5649 !Subtarget->isThumb1Only(); in LowerBR_CC()
5720 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) { in LowerBR_JT()
5728 if (isPositionIndependent() || Subtarget->isROPI()) { in LowerBR_JT()
5888 bool UseNEON = !InGPR && Subtarget->hasNEON(); in LowerFCOPYSIGN()
6092 const ARMSubtarget *Subtarget) const { in ExpandBITCAST()
6976 if (IsDouble && !Subtarget->hasFP64()) in LowerConstantFP()
7844 if (SDValue VCVT = LowerBuildVectorOfFPTrunc(Op, DAG, Subtarget)) in LowerBUILD_VECTOR()
7846 if (SDValue VCVT = LowerBuildVectorOfFPExt(Op, DAG, Subtarget)) in LowerBUILD_VECTOR()
8158 if (Cost <= 4 && (Subtarget->hasNEON() || isLegalMVEShuffleOp(PFEntry))) in isShuffleMaskLegal()
8173 else if (Subtarget->hasNEON() && in isShuffleMaskLegal()
8178 else if (Subtarget->hasNEON() && (VT == MVT::v8i16 || VT == MVT::v16i8) && in isShuffleMaskLegal()
8181 else if (Subtarget->hasMVEIntegerOps() && in isShuffleMaskLegal()
8752 if (Subtarget->hasMVEIntegerOps() && in LowerINSERT_VECTOR_ELT()
8754 return LowerINSERT_VECTOR_ELT_i1(Op, DAG, Subtarget); in LowerINSERT_VECTOR_ELT()
8955 const ARMSubtarget *Subtarget) { in LowerTruncate() argument
8956 if (!Subtarget->hasMVEIntegerOps()) in LowerTruncate()
8961 return LowerTruncatei1(N, DAG, Subtarget); in LowerTruncate()
9015 const ARMSubtarget *Subtarget) { in LowerVectorExtend() argument
9016 if (!Subtarget->hasMVEIntegerOps()) in LowerVectorExtend()
9564 assert(Subtarget->isTargetDarwin()); in LowerFSINCOS()
9582 bool ShouldUseSRet = Subtarget->isAPCS_ABI(); in LowerFSINCOS()
9808 if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() && in LowerLOAD()
9809 !Subtarget->isThumb1Only() && LD->isVolatile()) { in LowerLOAD()
9859 const ARMSubtarget *Subtarget) { in LowerSTORE() argument
9864 if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() && in LowerSTORE()
9865 !Subtarget->isThumb1Only() && ST->isVolatile()) { in LowerSTORE()
9881 } else if (Subtarget->hasMVEIntegerOps() && in LowerSTORE()
10009 const ARMSubtarget *Subtarget) { in ReplaceREADCYCLECOUNTER() argument
10135 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); in LowerOperation()
10136 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); in LowerOperation()
10149 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG, Subtarget); in LowerOperation()
10151 Subtarget); in LowerOperation()
10152 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG, Subtarget); in LowerOperation()
10155 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); in LowerOperation()
10162 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()
10163 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget); in LowerOperation()
10164 case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget); in LowerOperation()
10166 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget); in LowerOperation()
10167 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); in LowerOperation()
10168 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
10169 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG, Subtarget); in LowerOperation()
10171 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG, Subtarget); in LowerOperation()
10172 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget); in LowerOperation()
10173 case ISD::TRUNCATE: return LowerTruncate(Op.getNode(), DAG, Subtarget); in LowerOperation()
10175 case ISD::ZERO_EXTEND: return LowerVectorExtend(Op.getNode(), DAG, Subtarget); in LowerOperation()
10180 if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) in LowerOperation()
10182 return LowerSDIV(Op, DAG, Subtarget); in LowerOperation()
10184 if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) in LowerOperation()
10186 return LowerUDIV(Op, DAG, Subtarget); in LowerOperation()
10199 return LowerADDSUBSAT(Op, DAG, Subtarget); in LowerOperation()
10203 return LowerSTORE(Op, DAG, Subtarget); in LowerOperation()
10210 return LowerVecReduce(Op, DAG, Subtarget); in LowerOperation()
10215 return LowerVecReduceF(Op, DAG, Subtarget); in LowerOperation()
10222 if (Subtarget->isTargetWindows()) in LowerOperation()
10279 Res = ExpandBITCAST(N, DAG, Subtarget); in ReplaceNodeResults()
10284 Res = Expand64BitShift(N, DAG, Subtarget); in ReplaceNodeResults()
10301 Res = LowerADDSUBSAT(SDValue(N, 0), DAG, Subtarget); in ReplaceNodeResults()
10304 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget); in ReplaceNodeResults()
10308 assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows"); in ReplaceNodeResults()
10323 Res = LowerTruncate(N, DAG, Subtarget); in ReplaceNodeResults()
10327 Res = LowerVectorExtend(N, DAG, Subtarget); in ReplaceNodeResults()
10344 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() && in SetupEntryBlockForSjLj()
10346 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in SetupEntryBlockForSjLj()
10354 bool isThumb = Subtarget->isThumb(); in SetupEntryBlockForSjLj()
10355 bool isThumb2 = Subtarget->isThumb2(); in SetupEntryBlockForSjLj()
10470 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in EmitSjLjDispatchBlock()
10477 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass in EmitSjLjDispatchBlock()
10537 if (Subtarget->isThumb()) in EmitSjLjDispatchBlock()
10540 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP; in EmitSjLjDispatchBlock()
10575 if (Subtarget->isThumb2()) { in EmitSjLjDispatchBlock()
10631 } else if (Subtarget->isThumb()) { in EmitSjLjDispatchBlock()
10725 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) { in EmitSjLjDispatchBlock()
10852 if (Subtarget->isThumb2() && in EmitSjLjDispatchBlock()
10856 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg)) in EmitSjLjDispatchBlock()
10858 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg)) in EmitSjLjDispatchBlock()
11014 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in EmitStructByval()
11030 bool IsThumb1 = Subtarget->isThumb1Only(); in EmitStructByval()
11031 bool IsThumb2 = Subtarget->isThumb2(); in EmitStructByval()
11032 bool IsThumb = Subtarget->isThumb(); in EmitStructByval()
11041 Subtarget->hasNEON()) { in EmitStructByval()
11063 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) { in EmitStructByval()
11131 if (Subtarget->useMovt()) { in EmitStructByval()
11257 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in EmitLowered__chkstk()
11260 assert(Subtarget->isTargetWindows() && in EmitLowered__chkstk()
11262 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode"); in EmitLowered__chkstk()
11333 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in EmitLowered__dbzchk()
11538 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in EmitInstrWithCustomInserter()
11540 bool isThumb2 = Subtarget->isThumb2(); in EmitInstrWithCustomInserter()
11728 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); in EmitInstrWithCustomInserter()
11855 bool isThumb2 = Subtarget->isThumb2(); in EmitInstrWithCustomInserter()
11920 static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, in attachMEMCPYScratchRegs() argument
11922 bool isThumb1 = Subtarget->isThumb1Only(); in attachMEMCPYScratchRegs()
11948 attachMEMCPYScratchRegs(Subtarget, MI, Node); in AdjustInstrPostInstrSelection()
11964 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo(); in AdjustInstrPostInstrSelection()
11978 if (Subtarget->isThumb1Only()) { in AdjustInstrPostInstrSelection()
12032 if (!Subtarget->isThumb1Only()) in AdjustInstrPostInstrSelection()
12191 const ARMSubtarget *Subtarget) { in AddCombineToVPADD() argument
12219 const ARMSubtarget *Subtarget) { in AddCombineVUZPToVPADDL() argument
12272 const ARMSubtarget *Subtarget) { in AddCombineBUILD_VECTORToVPADDL() argument
12275 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
12376 const ARMSubtarget *Subtarget) { in AddCombineTo64BitSMLAL16() argument
12377 if (!Subtarget->hasBaseDSP()) in AddCombineTo64BitSMLAL16()
12453 const ARMSubtarget *Subtarget) { in AddCombineTo64bitMLAL() argument
12508 return AddCombineTo64BitSMLAL16(AddcSubcNode, AddeSubeNode, DCI, Subtarget); in AddCombineTo64bitMLAL()
12579 if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() && in AddCombineTo64bitMLAL()
12619 const ARMSubtarget *Subtarget) { in AddCombineTo64bitUMAAL() argument
12626 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in AddCombineTo64bitUMAAL()
12627 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
12644 return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget); in AddCombineTo64bitUMAAL()
12673 const ARMSubtarget *Subtarget) { in PerformUMLALCombine() argument
12674 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in PerformUMLALCombine()
12696 const ARMSubtarget *Subtarget) { in PerformAddcSubcCombine() argument
12710 if (Subtarget->isThumb1Only()) { in PerformAddcSubcCombine()
12729 const ARMSubtarget *Subtarget) { in PerformAddeSubeCombine() argument
12730 if (Subtarget->isThumb1Only()) { in PerformAddeSubeCombine()
12750 return AddCombineTo64bitMLAL(N, DCI, Subtarget); in PerformAddeSubeCombine()
12757 const ARMSubtarget *Subtarget) { in PerformSELECTCombine() argument
12758 if (!Subtarget->hasMVEIntegerOps()) in PerformSELECTCombine()
12973 const ARMSubtarget *Subtarget) { in PerformVSELECTCombine() argument
12974 if (!Subtarget->hasMVEIntegerOps()) in PerformVSELECTCombine()
13012 const ARMSubtarget *Subtarget) { in PerformABSCombine() argument
13031 const ARMSubtarget *Subtarget) { in PerformADDECombine() argument
13033 if (Subtarget->isThumb1Only()) in PerformADDECombine()
13034 return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformADDECombine()
13039 return AddCombineTo64bitUMAAL(N, DCI, Subtarget); in PerformADDECombine()
13048 const ARMSubtarget *Subtarget){ in PerformADDCombineWithOperands() argument
13050 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13054 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13057 Subtarget)) in PerformADDCombineWithOperands()
13068 const ARMSubtarget *Subtarget) { in PerformADDVecReduce() argument
13069 if (!Subtarget->hasMVEIntegerOps() || N->getValueType(0) != MVT::i64) in PerformADDVecReduce()
13159 if (Subtarget->isThumb1Only()) { in isDesirableToCommuteWithShift()
13188 if (!Subtarget->isThumb1Only()) in shouldFoldConstantShiftPairToMask()
13198 if (!Subtarget->hasNEON()) { in preferIncOfAddToSubOfNot()
13199 if (Subtarget->isThumb1Only()) in preferIncOfAddToSubOfNot()
13313 const ARMSubtarget *Subtarget) { in PerformADDCombine() argument
13318 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformADDCombine()
13321 if (SDValue Result = PerformADDVecReduce(N, DCI.DAG, Subtarget)) in PerformADDCombine()
13325 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
13329 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
13356 const ARMSubtarget *Subtarget) { in PerformSUBCombine() argument
13368 if (!Subtarget->hasMVEIntegerOps() || !N->getValueType(0).isVector()) in PerformSUBCombine()
13409 const ARMSubtarget *Subtarget) { in PerformVMULCombine() argument
13410 if (!Subtarget->hasVMLxForwarding()) in PerformVMULCombine()
13439 const ARMSubtarget *Subtarget) { in PerformMVEVMULLCombine() argument
13461 if (!Subtarget->isLittle()) in PerformMVEVMULLCombine()
13505 const ARMSubtarget *Subtarget) { in PerformMULCombine() argument
13509 if (Subtarget->hasMVEIntegerOps() && VT == MVT::v2i64) in PerformMULCombine()
13510 return PerformMVEVMULLCombine(N, DAG, Subtarget); in PerformMULCombine()
13512 if (Subtarget->isThumb1Only()) in PerformMULCombine()
13519 return PerformVMULCombine(N, DCI, Subtarget); in PerformMULCombine()
13591 const ARMSubtarget *Subtarget) { in CombineANDShift() argument
13695 const ARMSubtarget *Subtarget) { in PerformANDCombine() argument
13709 if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) && in PerformANDCombine()
13726 if (!Subtarget->isThumb1Only()) { in PerformANDCombine()
13731 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformANDCombine()
13735 if (Subtarget->isThumb1Only()) in PerformANDCombine()
13736 if (SDValue Result = CombineANDShift(N, DCI, Subtarget)) in PerformANDCombine()
13745 const ARMSubtarget *Subtarget) { in PerformORCombineToSMULWBT() argument
13746 if (!Subtarget->hasV6Ops() || in PerformORCombineToSMULWBT()
13747 (Subtarget->isThumb() && in PerformORCombineToSMULWBT()
13748 (!Subtarget->hasThumb2() || !Subtarget->hasDSP()))) in PerformORCombineToSMULWBT()
13805 const ARMSubtarget *Subtarget) { in PerformORCombineToBFI() argument
13807 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) in PerformORCombineToBFI()
13873 if (Subtarget->hasDSP() && in PerformORCombineToBFI()
13890 if (Subtarget->hasDSP() && in PerformORCombineToBFI()
13961 const ARMSubtarget *Subtarget) { in PerformORCombine_i1() argument
13988 const ARMSubtarget *Subtarget) { in PerformORCombine() argument
13998 if (Subtarget->hasMVEIntegerOps() && in PerformORCombine()
14000 return PerformORCombine_i1(N, DAG, Subtarget); in PerformORCombine()
14005 if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) && in PerformORCombine()
14022 if (!Subtarget->isThumb1Only()) { in PerformORCombine()
14026 if (SDValue Result = PerformORCombineToSMULWBT(N, DCI, Subtarget)) in PerformORCombine()
14034 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && in PerformORCombine()
14076 if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget)) in PerformORCombine()
14080 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformORCombine()
14088 const ARMSubtarget *Subtarget) { in PerformXORCombine() argument
14095 if (!Subtarget->isThumb1Only()) { in PerformXORCombine()
14100 if (SDValue Result = PerformSHLSimplify(N, DCI, Subtarget)) in PerformXORCombine()
14104 if (Subtarget->hasMVEIntegerOps()) { in PerformXORCombine()
14108 const TargetLowering *TLI = Subtarget->getTargetLowering(); in PerformXORCombine()
14268 const ARMSubtarget *Subtarget) { in PerformVMOVRRDCombine() argument
14271 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
14329 if (!Subtarget->isLittle() && BVSwap) in PerformVMOVRRDCombine()
14347 if (!Subtarget->isLittle() && BVSwap) in PerformVMOVRRDCombine()
14470 const ARMSubtarget *Subtarget) { in PerformBUILD_VECTORCombine() argument
14651 const ARMSubtarget *Subtarget) { in PerformVCMPCombine() argument
14652 if (!Subtarget->hasMVEIntegerOps()) in PerformVCMPCombine()
15425 const ARMSubtarget *Subtarget) { in PerformVDUPLANECombine() argument
15430 if (Subtarget->hasMVEIntegerOps()) { in PerformVDUPLANECombine()
15467 const ARMSubtarget *Subtarget) { in PerformVDUPCombine() argument
15471 if (Subtarget->hasMVEIntegerOps()) { in PerformVDUPCombine()
15482 if (!Subtarget->hasNEON()) in PerformVDUPCombine()
15775 const ARMSubtarget *Subtarget) { in PerformSTORECombine() argument
15782 if (Subtarget->hasNEON()) in PerformSTORECombine()
15786 if (Subtarget->hasMVEIntegerOps()) { in PerformSTORECombine()
15846 if (Subtarget->hasNEON() && ISD::isNormalStore(N) && VT.isVector() && in PerformSTORECombine()
15863 const ARMSubtarget *Subtarget) { in PerformVCVTCombine() argument
15864 if (!Subtarget->hasNEON()) in PerformVCVTCombine()
15920 const ARMSubtarget *Subtarget) { in PerformVDIVCombine() argument
15921 if (!Subtarget->hasNEON()) in PerformVDIVCombine()
16922 unsigned Heuristic = Subtarget->isThumb() ? 3 : 2; in PerformCMOVToBFICombine()
17186 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) { in PerformCMOVCombine()
17241 if (!Subtarget->isThumb1Only() && Subtarget->hasV5TOps()) { in PerformCMOVCombine()
17269 (!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) { in PerformCMOVCombine()
17282 (!Subtarget->isThumb1Only() || isPowerOf2Constant(FalseVal))) { in PerformCMOVCombine()
17311 if (Subtarget->isThumb1Only() && CC == ARMCC::NE && in PerformCMOVCombine()
17661 case ISD::SELECT: return PerformSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
17662 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()
17663 case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); in PerformDAGCombine()
17664 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
17665 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17666 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); in PerformDAGCombine()
17667 case ISD::SUB: return PerformSUBCombine(N, DCI, Subtarget); in PerformDAGCombine()
17668 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); in PerformDAGCombine()
17669 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); in PerformDAGCombine()
17670 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); in PerformDAGCombine()
17671 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); in PerformDAGCombine()
17673 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget); in PerformDAGCombine()
17675 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); in PerformDAGCombine()
17676 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); in PerformDAGCombine()
17678 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); in PerformDAGCombine()
17682 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget); in PerformDAGCombine()
17683 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); in PerformDAGCombine()
17686 return PerformExtractEltCombine(N, DCI, Subtarget); in PerformDAGCombine()
17689 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget); in PerformDAGCombine()
17690 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17693 return PerformVCVTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17695 return PerformVDIVCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17701 return PerformShiftCombine(N, DCI, Subtarget); in PerformDAGCombine()
17705 return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17707 return PerformFPExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17712 return PerformMinMaxCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17724 return PerformBITCASTCombine(N, DCI, Subtarget); in PerformDAGCombine()
17728 return PerformVECTOR_REG_CASTCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17735 return PerformVCMPCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17737 return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
17865 bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); in allowsMisalignedMemoryAccesses()
17872 *Fast = Subtarget->hasV7Ops(); in allowsMisalignedMemoryAccesses()
17881 if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) { in allowsMisalignedMemoryAccesses()
17888 if (!Subtarget->hasMVEIntegerOps()) in allowsMisalignedMemoryAccesses()
17931 if ((Op.isMemcpy() || Op.isZeroMemset()) && Subtarget->hasNEON() && in getOptimalMemOpType()
18006 return Subtarget->hasFullFP16(); in isFNegFree()
18037 if (Subtarget->hasNEON()) { in shouldSinkOperands()
18052 if (!Subtarget->hasMVEIntegerOps()) in shouldSinkOperands()
18147 if (!Subtarget->hasMVEIntegerOps()) in shouldConvertSplatType()
18170 if (Subtarget->hasMVEIntegerOps()) in isVectorLoadExtDesirable()
18208 if (Subtarget->hasFPAO()) in getScalingFactorCost()
18235 return Subtarget->hasMVEFloatOps(); in isFMAFasterThanFMulAndFAdd()
18237 return Subtarget->useFPVFMx16(); in isFMAFasterThanFMulAndFAdd()
18239 return Subtarget->useFPVFMx(); in isFMAFasterThanFMulAndFAdd()
18241 return Subtarget->useFPVFMx64(); in isFMAFasterThanFMulAndFAdd()
18276 const ARMSubtarget *Subtarget) { in isLegalT2AddressImmediate() argument
18279 if (VT.isVector() && Subtarget->hasNEON()) in isLegalT2AddressImmediate()
18281 if (VT.isVector() && VT.isFloatingPoint() && Subtarget->hasMVEIntegerOps() && in isLegalT2AddressImmediate()
18282 !Subtarget->hasMVEFloatOps()) in isLegalT2AddressImmediate()
18294 if (VT.isVector() && Subtarget->hasMVEIntegerOps()) { in isLegalT2AddressImmediate()
18310 if (VT.isFloatingPoint() && NumBytes == 2 && Subtarget->hasFPRegs16()) in isLegalT2AddressImmediate()
18313 if ((VT.isFloatingPoint() && Subtarget->hasVFP2Base()) || NumBytes == 8) in isLegalT2AddressImmediate()
18330 const ARMSubtarget *Subtarget) { in isLegalAddressImmediate() argument
18337 if (Subtarget->isThumb1Only()) in isLegalAddressImmediate()
18339 else if (Subtarget->isThumb2()) in isLegalAddressImmediate()
18340 return isLegalT2AddressImmediate(V, VT, Subtarget); in isLegalAddressImmediate()
18357 if (!Subtarget->hasVFP2Base()) // FIXME: NEON? in isLegalAddressImmediate()
18422 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
18440 if (Subtarget->isThumb1Only()) in isLegalAddressingMode()
18443 if (Subtarget->isThumb2()) in isLegalAddressingMode()
18486 if (!Subtarget->isThumb()) in isLegalICmpImmediate()
18489 if (Subtarget->isThumb2()) in isLegalICmpImmediate()
18503 if (!Subtarget->isThumb()) in isLegalAddImmediate()
18505 if (Subtarget->isThumb2()) in isLegalAddImmediate()
18656 if (Subtarget->isThumb1Only()) in getPreIndexedAddressParts()
18690 isLegal = Subtarget->hasMVEIntegerOps() && in getPreIndexedAddressParts()
18693 Subtarget->isLittle(), Base, Offset, isInc, DAG); in getPreIndexedAddressParts()
18695 if (Subtarget->isThumb2()) in getPreIndexedAddressParts()
18749 if (Subtarget->isThumb1Only()) { in getPostIndexedAddressParts()
18770 isLegal = Subtarget->hasMVEIntegerOps() && in getPostIndexedAddressParts()
18772 Subtarget->isLittle(), Base, Offset, in getPostIndexedAddressParts()
18775 if (Subtarget->isThumb2()) in getPostIndexedAddressParts()
18789 !Subtarget->isThumb2()) in getPostIndexedAddressParts()
19039 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()
19076 if (!Subtarget->hasVFP2Base()) in LowerXConstraint()
19080 if (ConstraintVT.isVector() && Subtarget->hasNEON() && in LowerXConstraint()
19137 if (Subtarget->isThumb()) in getSingleConstraintMatchWeight()
19160 if (Subtarget->isThumb()) in getRegForInlineAsmConstraint()
19164 if (Subtarget->isThumb()) in getRegForInlineAsmConstraint()
19168 if (Subtarget->isThumb1Only()) in getRegForInlineAsmConstraint()
19259 if (Subtarget->hasV6T2Ops() || (Subtarget->hasV8MBaselineOps())) in LowerAsmOperandForConstraint()
19264 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19269 } else if (Subtarget->isThumb2()) { in LowerAsmOperandForConstraint()
19283 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19300 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19307 } else if (Subtarget->isThumb2()) { in LowerAsmOperandForConstraint()
19327 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19332 } else if (Subtarget->isThumb2()) { in LowerAsmOperandForConstraint()
19352 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19367 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19375 if (Subtarget->isThumb1Only()) { in LowerAsmOperandForConstraint()
19413 const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget) { in getDivRemArgList() argument
19430 if (Subtarget->isTargetWindows() && Args.size() >= 2) in getDivRemArgList()
19436 assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() || in LowerDivRem()
19437 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() || in LowerDivRem()
19438 Subtarget->isTargetWindows()) && in LowerDivRem()
19453 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode() in LowerDivRem()
19454 : Subtarget->hasDivideInARMMode(); in LowerDivRem()
19474 Subtarget); in LowerDivRem()
19481 if (Subtarget->isTargetWindows()) in LowerDivRem()
19517 Subtarget); in LowerREM()
19522 if (Subtarget->isTargetWindows()) in LowerREM()
19540 assert(Subtarget->isTargetWindows() && "unsupported target platform"); in LowerDYNAMIC_STACKALLOC()
19588 assert((!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) && in LowerFP_EXTEND()
19591 assert(!(DstSz == 32 && Subtarget->hasFP16()) && in LowerFP_EXTEND()
19595 if (SrcSz == 32 && DstSz == 64 && Subtarget->hasFP64()) { in LowerFP_EXTEND()
19616 bool Supported = (Sz == 16 ? Subtarget->hasFP16() : Subtarget->hasFP64()); in LowerFP_EXTEND()
19651 assert((!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) && in LowerFP_ROUND()
19657 if (SrcSz == 32 && Subtarget->hasFP16()) in LowerFP_ROUND()
19724 if (!Subtarget->hasVFP3Base()) in isFPImmLegal()
19726 if (VT == MVT::f16 && Subtarget->hasFullFP16()) in isFPImmLegal()
19728 if (VT == MVT::f32 && Subtarget->hasFullFP16() && in isFPImmLegal()
19733 if (VT == MVT::f64 && Subtarget->hasFP64()) in isFPImmLegal()
19995 if (!Subtarget->hasDataBarrier()) { in makeDMB()
19999 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { in makeDMB()
20013 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; in makeDMB()
20036 if (Subtarget->preferISHSTBarriers()) in emitLeadingFence()
20069 return (Size == 64) && !Subtarget->isMClass(); in shouldExpandAtomicStoreInIR()
20082 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly in shouldExpandAtomicLoadInIR()
20102 bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps(); in shouldExpandAtomicRMWInIR()
20103 return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW) in shouldExpandAtomicRMWInIR()
20119 !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps(); in shouldExpandAtomicCmpXchgInIR()
20121 Size <= (Subtarget->isMClass() ? 32U : 64U)) in shouldExpandAtomicCmpXchgInIR()
20133 return Subtarget->isTargetMachO(); in useLoadStackGuardNode()
20137 if (!Subtarget->getTargetTriple().isWindowsMSVCEnvironment()) in insertSSPDeclarations()
20154 if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment()) in getSDagStackGuard()
20161 if (Subtarget->getTargetTriple().isWindowsMSVCEnvironment()) in getSSPStackGuardCheck()
20169 if (!Subtarget->hasNEON()) in canCombineStoreAndExtract()
20196 return Subtarget->hasV6T2Ops(); in isCheapToSpeculateCttz()
20200 return Subtarget->hasV6T2Ops(); in isCheapToSpeculateCtlz()
20204 return !Subtarget->hasMinSize() || Subtarget->isTargetWindows(); in shouldExpandShift()
20226 if (!Subtarget->isLittle()) in emitLoadLinked()
20243 if (!Subtarget->hasV7Ops()) in emitAtomicCmpXchgNoStoreLLBalance()
20266 if (!Subtarget->isLittle()) in emitStoreConditional()
20284 return Subtarget->isMClass(); in alignLoopsWithOptSize()
20302 if (!Subtarget->hasNEON() && !Subtarget->hasMVEIntegerOps()) in isLegalInterleavedAccessType()
20308 if (Subtarget->hasNEON() && VecTy->getElementType()->isHalfTy()) in isLegalInterleavedAccessType()
20310 if (Subtarget->hasMVEIntegerOps() && Factor == 3) in isLegalInterleavedAccessType()
20321 if (Subtarget->hasMVEIntegerOps() && Alignment < ElSize / 8) in isLegalInterleavedAccessType()
20326 if (Subtarget->hasNEON() && VecSize == 64) in isLegalInterleavedAccessType()
20332 if (Subtarget->hasNEON()) in getMaxSupportedInterleaveFactor()
20334 if (Subtarget->hasMVEIntegerOps()) in getMaxSupportedInterleaveFactor()
20400 if (Subtarget->hasNEON()) { in lowerInterleavedLoad()
20568 if (Subtarget->hasNEON()) { in lowerInterleavedStore()
20739 return Subtarget->useSjLjEH() ? Register() : ARM::R0; in getExceptionPointerRegister()
20746 return Subtarget->useSjLjEH() ? Register() : ARM::R1; in getExceptionSelectorRegister()
20758 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo(); in insertCopiesSplitCSR()
20763 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in insertCopiesSplitCSR()