Lines Matching refs:Subtarget
70 if (Subtarget.isGP64bit()) in MipsSETargetLowering()
73 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { in MipsSETargetLowering()
85 if (Subtarget.hasDSP()) { in MipsSETargetLowering()
108 if (Subtarget.hasMips32r2()) { in MipsSETargetLowering()
114 if (Subtarget.hasDSPR2()) in MipsSETargetLowering()
117 if (Subtarget.hasMSA()) { in MipsSETargetLowering()
171 if (!Subtarget.useSoftFloat()) { in MipsSETargetLowering()
175 if (!Subtarget.isSingleFloat()) { in MipsSETargetLowering()
176 if (Subtarget.isFP64bit()) in MipsSETargetLowering()
188 if (Subtarget.hasCnMips()) in MipsSETargetLowering()
190 else if (Subtarget.isGP64bit()) in MipsSETargetLowering()
193 if (Subtarget.isGP64bit()) { in MipsSETargetLowering()
217 if (Subtarget.hasMips32r2() && !Subtarget.useSoftFloat() && in MipsSETargetLowering()
218 !Subtarget.hasMips64()) { in MipsSETargetLowering()
227 if (Subtarget.hasMips32r6()) { in MipsSETargetLowering()
255 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6"); in MipsSETargetLowering()
274 if (Subtarget.hasMips64r6()) { in MipsSETargetLowering()
299 computeRegisterProperties(Subtarget.getRegisterInfo()); in MipsSETargetLowering()
311 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; in getRepRegClassFor()
410 if(!Subtarget.hasMips32r6()) in lowerSELECT()
428 if (Subtarget.systemSupportsUnalignedAccess()) { in allowsMisalignedMemoryAccesses()
484 const MipsSubtarget &Subtarget) { in performANDCombine() argument
485 if (!Subtarget.hasMSA()) in performANDCombine()
599 const MipsSubtarget &Subtarget) { in performORCombine() argument
600 if (!Subtarget.hasMSA()) in performORCombine()
616 bool IsLittleEndian = !Subtarget.isLittle(); in performORCombine()
719 const MipsSubtarget &Subtarget) { in shouldTransformMulToShiftsAddsSubs() argument
745 unsigned MaxSteps = Subtarget.isABI_O32() ? 8 : 12; in shouldTransformMulToShiftsAddsSubs()
832 const MipsSubtarget &Subtarget) { in performMULCombine() argument
837 C->getAPIntValue(), VT, DAG, Subtarget)) in performMULCombine()
847 const MipsSubtarget &Subtarget) { in performDSPShiftCombine() argument
855 if (!Subtarget.hasDSP()) in performDSPShiftCombine()
860 EltSize, !Subtarget.isLittle()) || in performDSPShiftCombine()
872 const MipsSubtarget &Subtarget) { in performSHLCombine() argument
878 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); in performSHLCombine()
895 const MipsSubtarget &Subtarget) { in performSRACombine() argument
898 if (Subtarget.hasMSA()) { in performSRACombine()
932 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) in performSRACombine()
935 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); in performSRACombine()
941 const MipsSubtarget &Subtarget) { in performSRLCombine() argument
944 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine()
947 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); in performSRLCombine()
999 const MipsSubtarget &Subtarget) { in performXORCombine() argument
1002 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { in performXORCombine()
1032 Val = performANDCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1035 Val = performORCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1038 return performMULCombine(N, DAG, DCI, this, Subtarget); in PerformDAGCombine()
1040 Val = performSHLCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1043 return performSRACombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1045 return performSRLCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
1049 Val = performXORCombine(N, DAG, Subtarget); in PerformDAGCombine()
1195 if (!Subtarget.isLittle()) in lowerLOAD()
1218 if (!Subtarget.isLittle()) in lowerSTORE()
1267 assert(!Subtarget.hasMips32r6()); in lowerMulDiv()
1667 !Subtarget.isLittle()); in lowerINTRINSIC_WO_CHAIN()
1703 !Subtarget.isLittle()); in lowerINTRINSIC_WO_CHAIN()
1778 if (Subtarget.hasMips64()) in lowerINTRINSIC_WO_CHAIN()
1793 if (Subtarget.hasMips64()) in lowerINTRINSIC_WO_CHAIN()
2294 const MipsSubtarget &Subtarget) { in lowerMSALoadIntr() argument
2305 if (Subtarget.isABI_N64()) in lowerMSALoadIntr()
2363 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget); in lowerINTRINSIC_W_CHAIN()
2368 const MipsSubtarget &Subtarget) { in lowerMSAStoreIntr() argument
2379 if (Subtarget.isABI_N64()) in lowerMSAStoreIntr()
2398 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget); in lowerINTRINSIC_VOID()
2468 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) in lowerBUILD_VECTOR()
2473 !Subtarget.isLittle()) && SplatBitSize <= 64) { in lowerBUILD_VECTOR()
3037 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitBPOSGE32()
3106 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitMSACBranchPseudo()
3171 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitCOPY_FW()
3180 if (!Subtarget.useOddSPReg()) { in emitCOPY_FW()
3191 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass in emitCOPY_FW()
3215 assert(Subtarget.isFP64bit()); in emitCOPY_FD()
3217 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitCOPY_FD()
3246 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitINSERT_FW()
3254 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass in emitINSERT_FW()
3280 assert(Subtarget.isFP64bit()); in emitINSERT_FD()
3282 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitINSERT_FD()
3328 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitINSERT_DF_VIDX()
3339 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3340 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX()
3341 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX()
3419 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB), in emitINSERT_DF_VIDX()
3421 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO) in emitINSERT_DF_VIDX()
3442 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFILL_FW()
3448 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass in emitFILL_FW()
3451 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass in emitFILL_FW()
3475 assert(Subtarget.isFP64bit()); in emitFILL_FD()
3477 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFILL_FD()
3511 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitST_F16_PSEUDO()
3524 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitST_F16_PSEUDO()
3566 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitLD_F16_PSEUDO()
3576 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitLD_F16_PSEUDO()
3656 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); in emitFPROUND_PSEUDO()
3658 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; in emitFPROUND_PSEUDO()
3659 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64; in emitFPROUND_PSEUDO()
3661 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFPROUND_PSEUDO()
3761 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); in emitFPEXTEND_PSEUDO()
3763 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; in emitFPEXTEND_PSEUDO()
3764 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64; in emitFPEXTEND_PSEUDO()
3766 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFPEXTEND_PSEUDO()
3819 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFEXP2_W_1()
3848 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitFEXP2_D_1()