Lines Matching refs:Subtarget
47 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
49 if (Subtarget.isRV32E()) in RISCVTargetLowering()
52 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
56 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
60 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
62 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
66 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
81 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
86 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
88 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
90 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
110 if (Subtarget.hasStdExtV()) { in RISCVTargetLowering()
132 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
136 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
140 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
144 if (Subtarget.useRVVForFixedLengthVectors()) { in RISCVTargetLowering()
148 const RISCVRegisterInfo &TRI = *Subtarget.getRegisterInfo(); in RISCVTargetLowering()
186 if (!Subtarget.hasStdExtZbb()) { in RISCVTargetLowering()
191 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
204 if (!Subtarget.hasStdExtM()) { in RISCVTargetLowering()
213 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
240 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in RISCVTargetLowering()
241 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
250 if (Subtarget.hasStdExtZbp()) { in RISCVTargetLowering()
260 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
268 Subtarget.hasStdExtZbb() ? Legal : Expand); in RISCVTargetLowering()
271 if (Subtarget.hasStdExtZbb()) { in RISCVTargetLowering()
277 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
289 if (Subtarget.hasStdExtZbt()) { in RISCVTargetLowering()
294 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
311 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
314 if (Subtarget.hasStdExtZfh()) { in RISCVTargetLowering()
330 if (Subtarget.hasStdExtF()) { in RISCVTargetLowering()
348 if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) in RISCVTargetLowering()
351 if (Subtarget.hasStdExtD()) { in RISCVTargetLowering()
371 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
378 if (Subtarget.hasStdExtF()) { in RISCVTargetLowering()
393 Subtarget.is64Bit() ? Legal : Custom); in RISCVTargetLowering()
398 if (Subtarget.is64Bit()) in RISCVTargetLowering()
401 if (Subtarget.hasStdExtA()) { in RISCVTargetLowering()
402 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
410 if (Subtarget.hasStdExtV()) { in RISCVTargetLowering()
421 if (Subtarget.is64Bit()) { in RISCVTargetLowering()
438 if (!Subtarget.is64Bit()) { in RISCVTargetLowering()
641 if (Subtarget.hasStdExtZfh()) in RISCVTargetLowering()
646 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
652 if (Subtarget.hasStdExtD()) in RISCVTargetLowering()
658 if (Subtarget.useRVVForFixedLengthVectors()) { in RISCVTargetLowering()
715 if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) { in RISCVTargetLowering()
846 const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); in RISCVTargetLowering()
863 if (Subtarget.hasStdExtV()) { in RISCVTargetLowering()
878 if (Subtarget.hasStdExtV() && in getSetCCResultType()
879 (VT.isScalableVector() || Subtarget.useRVVForFixedLengthVectors())) in getSetCCResultType()
885 return Subtarget.getXLenVT(); in getVPExplicitVectorLengthTy()
955 if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) in isTruncateFree()
963 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || in isTruncateFree()
976 (Subtarget.is64Bit() && MemVT == MVT::i32)) && in isZExtFree()
986 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
990 return Subtarget.hasStdExtZbb(); in isCheapToSpeculateCttz()
994 return Subtarget.hasStdExtZbb(); in isCheapToSpeculateCtlz()
999 if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) in isFPImmLegal()
1001 if (VT == MVT::f32 && !Subtarget.hasStdExtF()) in isFPImmLegal()
1003 if (VT == MVT::f64 && !Subtarget.hasStdExtD()) in isFPImmLegal()
1011 return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || in hasBitPreservingFPLogic()
1012 (VT == MVT::f32 && Subtarget.hasStdExtF()) || in hasBitPreservingFPLogic()
1013 (VT == MVT::f64 && Subtarget.hasStdExtD()); in hasBitPreservingFPLogic()
1021 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getRegisterTypeForCallingConv()
1032 if (VT == MVT::f16 && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfh()) in getNumRegistersForCallingConv()
1205 return !Subtarget.useRVVForFixedLengthVectors() || in mergeStoresAfterLegalization()
1210 const RISCVSubtarget &Subtarget) { in useRVVForFixedLengthVectorVT() argument
1212 if (!Subtarget.useRVVForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
1222 unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits(); in useRVVForFixedLengthVectorVT()
1241 if (!Subtarget.hasStdExtZfh()) in useRVVForFixedLengthVectorVT()
1245 if (!Subtarget.hasStdExtF()) in useRVVForFixedLengthVectorVT()
1249 if (!Subtarget.hasStdExtD()) in useRVVForFixedLengthVectorVT()
1256 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
1268 return ::useRVVForFixedLengthVectorVT(VT, Subtarget); in useRVVForFixedLengthVectorVT()
1273 const RISCVSubtarget &Subtarget) { in getContainerForFixedLengthVector() argument
1276 useRVVForFixedLengthVectorVT(VT, Subtarget)) && in getContainerForFixedLengthVector()
1279 unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits(); in getContainerForFixedLengthVector()
1304 const RISCVSubtarget &Subtarget) { in getContainerForFixedLengthVector() argument
1306 Subtarget); in getContainerForFixedLengthVector()
1315 const RISCVSubtarget &Subtarget) { in convertToScalableVector() argument
1321 SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in convertToScalableVector()
1327 const RISCVSubtarget &Subtarget) { in convertFromScalableVector() argument
1333 SDValue Zero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in convertFromScalableVector()
1342 const RISCVSubtarget &Subtarget) { in getDefaultVLOps() argument
1344 MVT XLenVT = Subtarget.getXLenVT(); in getDefaultVLOps()
1356 const RISCVSubtarget &Subtarget) { in getDefaultScalableVLOps() argument
1358 return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget); in getDefaultScalableVLOps()
1383 const RISCVSubtarget &Subtarget) { in lowerSPLAT_VECTOR() argument
1387 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerSPLAT_VECTOR()
1391 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerSPLAT_VECTOR()
1396 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerSPLAT_VECTOR()
1472 const RISCVSubtarget &Subtarget) { in lowerBUILD_VECTOR() argument
1476 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerBUILD_VECTOR()
1480 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerBUILD_VECTOR()
1482 MVT XLenVT = Subtarget.getXLenVT(); in lowerBUILD_VECTOR()
1488 return convertFromScalableVector(VT, VMClr, DAG, Subtarget); in lowerBUILD_VECTOR()
1493 return convertFromScalableVector(VT, VMSet, DAG, Subtarget); in lowerBUILD_VECTOR()
1505 std::min(std::max(NumElts, 8u), Subtarget.getXLen()); in lowerBUILD_VECTOR()
1595 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerBUILD_VECTOR()
1612 VID = convertFromScalableVector(VT, VID, DAG, Subtarget); in lowerBUILD_VECTOR()
1671 if (Subtarget.is64Bit() && ViaIntVT == MVT::i32) in lowerBUILD_VECTOR()
1678 (!Subtarget.is64Bit() && ViaIntVT == MVT::i64)) && in lowerBUILD_VECTOR()
1684 getContainerForFixedLengthVector(DAG, ViaVecVT, Subtarget); in lowerBUILD_VECTOR()
1688 Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget); in lowerBUILD_VECTOR()
1797 const RISCVSubtarget &Subtarget) { in lowerScalarSplat() argument
1801 MVT XLenVT = Subtarget.getXLenVT(); in lowerScalarSplat()
1823 const RISCVSubtarget &Subtarget) { in lowerVECTOR_SHUFFLE() argument
1827 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECTOR_SHUFFLE()
1832 MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); in lowerVECTOR_SHUFFLE()
1835 std::tie(TrueMask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1874 return convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1895 return convertFromScalableVector(VT, Splat, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1898 V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1903 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1983 Gather = lowerScalarSplat(SplatValue, VL, ContainerVT, DL, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1987 convertToScalableVector(IndexContainerVT, LHSIndices, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1989 V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
1999 convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2003 convertToScalableVector(IndexContainerVT, RHSIndices, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2005 V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2011 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2016 const RISCVSubtarget &Subtarget) { in getRVVFPExtendOrRound() argument
2022 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in getRVVFPExtendOrRound()
2125 MVT XLenVT = Subtarget.getXLenVT(); in LowerOperation()
2151 if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) { in LowerOperation()
2156 if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
2157 Subtarget.hasStdExtF()) { in LowerOperation()
2172 assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); in LowerOperation()
2186 assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization"); in LowerOperation()
2192 unsigned ShAmtWidth = Subtarget.getXLen() - 1; in LowerOperation()
2226 Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget); in LowerOperation()
2232 getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2243 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in LowerOperation()
2312 Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget); in LowerOperation()
2322 Src = getRVVFPExtendOrRound(Src, VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2323 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2329 Src, InterVT, InterContainerVT, DL, DAG, Subtarget); in LowerOperation()
2332 DL, DAG, Subtarget); in LowerOperation()
2334 return convertFromScalableVector(VT, Extend, DAG, Subtarget); in LowerOperation()
2352 Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget); in LowerOperation()
2362 Src = getRVVFPExtendOrRound(Src, VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2363 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2367 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2373 DL, DAG, Subtarget); in LowerOperation()
2376 return convertFromScalableVector(VT, Round, DAG, Subtarget); in LowerOperation()
2476 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in LowerOperation()
2478 Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget); in LowerOperation()
2480 return convertFromScalableVector(VT, Src, DAG, Subtarget); in LowerOperation()
2508 return lowerBUILD_VECTOR(Op, DAG, Subtarget); in LowerOperation()
2512 return lowerSPLAT_VECTOR(Op, DAG, Subtarget); in LowerOperation()
2514 return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
2579 assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() && in LowerOperation()
2738 MVT XLenVT = Subtarget.getXLenVT(); in lowerGlobalAddress()
2781 MVT XLenVT = Subtarget.getXLenVT(); in getStaticTLSAddr()
2854 MVT XLenVT = Subtarget.getXLenVT(); in lowerGlobalTLSAddress()
2892 MVT XLenVT = Subtarget.getXLenVT(); in lowerSELECT()
2954 MVT XLenVT = Subtarget.getXLenVT(); in lowerBRCOND()
2991 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerFRAMEADDR()
2996 int XLenInBytes = Subtarget.getXLen() / 8; in lowerFRAMEADDR()
3014 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerRETURNADDR()
3018 MVT XLenVT = Subtarget.getXLenVT(); in lowerRETURNADDR()
3019 int XLenInBytes = Subtarget.getXLen() / 8; in lowerRETURNADDR()
3059 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftLeftParts()
3060 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftLeftParts()
3109 SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); in lowerShiftRightParts()
3110 SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); in lowerShiftRightParts()
3142 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
3146 SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second; in lowerVectorMaskSplat()
3149 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskSplat()
3168 assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 && in lowerSPLAT_VECTOR_PARTS()
3180 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerSPLAT_VECTOR_PARTS()
3183 return convertFromScalableVector(VecVT, Res, DAG, Subtarget); in lowerSPLAT_VECTOR_PARTS()
3219 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskExt()
3229 !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; in lowerVectorMaskExt()
3247 SDValue CC = convertToScalableVector(I1ContainerVT, Src, DAG, Subtarget); in lowerVectorMaskExt()
3250 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskExt()
3258 return convertFromScalableVector(VecVT, Select, DAG, Subtarget); in lowerVectorMaskExt()
3278 convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
3282 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
3286 return convertFromScalableVector(ExtVT, Ext, DAG, Subtarget); in lowerFixedLengthVectorExtendToRVV()
3306 Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget); in lowerVectorMaskTrunc()
3309 SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT()); in lowerVectorMaskTrunc()
3310 SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); in lowerVectorMaskTrunc()
3321 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskTrunc()
3328 return convertFromScalableVector(MaskVT, Trunc, DAG, Subtarget); in lowerVectorMaskTrunc()
3358 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
3361 MVT XLenVT = Subtarget.getXLenVT(); in lowerINSERT_VECTOR_ELT()
3364 bool IsLegalInsert = Subtarget.is64Bit() || Val.getValueType() != MVT::i64; in lowerINSERT_VECTOR_ELT()
3378 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
3389 return convertFromScalableVector(VecVT, Vec, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
3404 getDefaultScalableVLOps(I32ContainerVT, DL, DAG, Subtarget).first; in lowerINSERT_VECTOR_ELT()
3427 return convertFromScalableVector(VecVT, Slideup, DAG, Subtarget); in lowerINSERT_VECTOR_ELT()
3441 MVT XLenVT = Subtarget.getXLenVT(); in lowerEXTRACT_VECTOR_ELT()
3455 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerEXTRACT_VECTOR_ELT()
3481 const RISCVSubtarget &Subtarget) { in lowerVectorIntrinsicSplats() argument
3486 if (!Subtarget.hasStdExtV()) in lowerVectorIntrinsicSplats()
3504 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorIntrinsicSplats()
3558 MVT XLenVT = Subtarget.getXLenVT(); in LowerINTRINSIC_WO_CHAIN()
3595 Op.getSimpleValueType(), DL, DAG, Subtarget); in LowerINTRINSIC_WO_CHAIN()
3708 return lowerVectorIntrinsicSplats(Op, DAG, Subtarget); in LowerINTRINSIC_WO_CHAIN()
3713 return lowerVectorIntrinsicSplats(Op, DAG, Subtarget); in LowerINTRINSIC_W_CHAIN()
3757 MVT XLenVT = Subtarget.getXLenVT(); in lowerVectorMaskVECREDUCE()
3764 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerVectorMaskVECREDUCE()
3768 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVectorMaskVECREDUCE()
3823 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerVECREDUCE()
3829 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerVECREDUCE()
3839 DAG.getConstant(0, DL, Subtarget.getXLenVT())); in lowerVECREDUCE()
3884 VectorVal = convertToScalableVector(ContainerVT, VectorVal, DAG, Subtarget); in lowerFPVECREDUCE()
3890 std::tie(Mask, VL) = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget); in lowerFPVECREDUCE()
3898 DAG.getConstant(0, DL, Subtarget.getXLenVT())); in lowerFPVECREDUCE()
3909 MVT XLenVT = Subtarget.getXLenVT(); in lowerINSERT_SUBVECTOR()
3911 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerINSERT_SUBVECTOR()
3961 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
3967 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first; in lowerINSERT_SUBVECTOR()
3976 Slideup = convertFromScalableVector(VecVT, Slideup, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
4026 std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget); in lowerINSERT_SUBVECTOR()
4058 MVT XLenVT = Subtarget.getXLenVT(); in lowerEXTRACT_SUBVECTOR()
4060 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerEXTRACT_SUBVECTOR()
4112 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in lowerEXTRACT_SUBVECTOR()
4115 getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first; in lowerEXTRACT_SUBVECTOR()
4160 std::tie(Mask, VL) = getDefaultScalableVLOps(InterSubVT, DL, DAG, Subtarget); in lowerEXTRACT_SUBVECTOR()
4181 MVT XLenVT = Subtarget.getXLenVT(); in lowerSTEP_VECTOR()
4183 std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); in lowerSTEP_VECTOR()
4195 DL, DAG, Subtarget); in lowerSTEP_VECTOR()
4215 unsigned VectorBitsMax = Subtarget.getMaxRVVVectorSizeInBits(); in lowerVECTOR_REVERSE()
4253 MVT XLenVT = Subtarget.getXLenVT(); in lowerVECTOR_REVERSE()
4255 std::tie(Mask, VL) = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget); in lowerVECTOR_REVERSE()
4266 !Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64; in lowerVECTOR_REVERSE()
4295 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorLoadToRVV()
4302 SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerFixedLengthVectorLoadToRVV()
4331 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorStoreToRVV()
4334 convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget); in lowerFixedLengthVectorStoreToRVV()
4346 MVT XLenVT = Subtarget.getXLenVT(); in lowerMLOAD()
4357 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMLOAD()
4358 PassThru = convertToScalableVector(ContainerVT, PassThru, DAG, Subtarget); in lowerMLOAD()
4373 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMLOAD()
4385 MVT XLenVT = Subtarget.getXLenVT(); in lowerMSTORE()
4393 Val = convertToScalableVector(ContainerVT, Val, DAG, Subtarget); in lowerMSTORE()
4394 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMSTORE()
4415 convertToScalableVector(ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
4417 convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
4421 DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT()); in lowerFixedLengthVectorSetccToRVV()
4429 return convertFromScalableVector(VT, Cmp, DAG, Subtarget); in lowerFixedLengthVectorSetccToRVV()
4465 X = convertToScalableVector(ContainerVT, X, DAG, Subtarget); in lowerABS()
4468 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerABS()
4472 DAG.getConstant(0, DL, Subtarget.getXLenVT())); in lowerABS()
4478 return convertFromScalableVector(VT, Max, DAG, Subtarget); in lowerABS()
4491 Mag = convertToScalableVector(ContainerVT, Mag, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4492 Sign = convertToScalableVector(ContainerVT, Sign, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4495 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4500 return convertFromScalableVector(VT, CopySign, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
4512 convertToScalableVector(I1ContainerVT, Op.getOperand(0), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4514 convertToScalableVector(ContainerVT, Op.getOperand(1), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4516 convertToScalableVector(ContainerVT, Op.getOperand(2), DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4520 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4525 return convertFromScalableVector(VT, Select, DAG, Subtarget); in lowerFixedLengthVectorSelectToRVV()
4548 Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget)); in lowerToScalableOp()
4553 std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); in lowerToScalableOp()
4559 return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget); in lowerToScalableOp()
4586 Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget)); in lowerVPOp()
4596 return convertFromScalableVector(VT, VPOp, DAG, Subtarget); in lowerVPOp()
4614 MVT XLenVT = Subtarget.getXLenVT(); in lowerMGATHER()
4643 Index = convertToScalableVector(IndexVT, Index, DAG, Subtarget); in lowerMGATHER()
4648 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMGATHER()
4649 PassThru = convertToScalableVector(ContainerVT, PassThru, DAG, Subtarget); in lowerMGATHER()
4675 Result = convertFromScalableVector(VT, Result, DAG, Subtarget); in lowerMGATHER()
4695 MVT XLenVT = Subtarget.getXLenVT(); in lowerMSCATTER()
4724 Index = convertToScalableVector(IndexVT, Index, DAG, Subtarget); in lowerMSCATTER()
4725 Val = convertToScalableVector(ContainerVT, Val, DAG, Subtarget); in lowerMSCATTER()
4730 Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget); in lowerMSCATTER()
4754 const MVT XLenVT = Subtarget.getXLenVT(); in lowerGET_ROUNDING()
4785 const MVT XLenVT = Subtarget.getXLenVT(); in lowerSET_ROUNDING()
4881 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
4921 assert(!Subtarget.is64Bit() && in ReplaceNodeResults()
4935 unsigned XLen = Subtarget.getXLen(); in ReplaceNodeResults()
4950 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
4974 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
4983 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
4991 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
4999 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5016 Subtarget.is64Bit() && Subtarget.hasStdExtM() && in ReplaceNodeResults()
5037 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5061 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5063 if (Subtarget.hasStdExtZbb()) { in ReplaceNodeResults()
5086 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
5087 if (VT == MVT::i16 && Op0VT == MVT::f16 && Subtarget.hasStdExtZfh()) { in ReplaceNodeResults()
5090 } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5091 Subtarget.hasStdExtF()) { in ReplaceNodeResults()
5110 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5129 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5145 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
5147 (VT == MVT::i32 && Subtarget.is64Bit())) && in ReplaceNodeResults()
5148 Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); in ReplaceNodeResults()
5154 unsigned Opc = Subtarget.is64Bit() ? RISCVISD::GREVW : RISCVISD::GREV; in ReplaceNodeResults()
5164 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5165 Subtarget.hasStdExtZbt() && "Unexpected custom legalisation"); in ReplaceNodeResults()
5200 assert(!Subtarget.is64Bit() && N->getValueType(0) == MVT::i64 && in ReplaceNodeResults()
5208 Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); in ReplaceNodeResults()
5211 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
5252 Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC; in ReplaceNodeResults()
5260 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5274 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5294 assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && in ReplaceNodeResults()
5309 MVT XLenVT = Subtarget.getXLenVT(); in ReplaceNodeResults()
5313 Subtarget.getXLenVT(), N->getOperand(1)); in ReplaceNodeResults()
5318 assert(VT == MVT::i64 && !Subtarget.is64Bit() && in ReplaceNodeResults()
5358 SDVTList VTs = DAG.getVTList(Subtarget.getXLenVT(), MVT::Other); in ReplaceNodeResults()
5482 const RISCVSubtarget &Subtarget) { in combineORToGREV() argument
5483 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToGREV()
5486 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGREV()
5508 const RISCVSubtarget &Subtarget) { in combineORToGORC() argument
5509 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToGORC()
5512 if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { in combineORToGORC()
5587 const RISCVSubtarget &Subtarget) { in combineORToSHFL() argument
5588 assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson"); in combineORToSHFL()
5591 if (VT != MVT::i32 && VT != Subtarget.getXLenVT()) in combineORToSHFL()
5750 const RISCVSubtarget &Subtarget) { in performANDCombine() argument
5759 const RISCVSubtarget &Subtarget) { in performORCombine() argument
5761 if (Subtarget.hasStdExtZbp()) { in performORCombine()
5762 if (auto GREV = combineORToGREV(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
5764 if (auto GORC = combineORToGORC(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
5766 if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget)) in performORCombine()
5777 const RISCVSubtarget &Subtarget) { in performXORCombine() argument
5792 const RISCVSubtarget &Subtarget) { in performANY_EXTENDCombine() argument
5793 if (!Subtarget.is64Bit()) in performANY_EXTENDCombine()
5809 if (!Subtarget.hasStdExtM()) in performANY_EXTENDCombine()
6088 return performANDCombine(N, DCI, Subtarget); in PerformDAGCombine()
6090 return performORCombine(N, DCI, Subtarget); in PerformDAGCombine()
6092 return performXORCombine(N, DCI, Subtarget); in PerformDAGCombine()
6094 return performANY_EXTENDCombine(N, DCI, Subtarget); in PerformDAGCombine()
6099 if (N->getValueType(0) == MVT::i64 && Subtarget.is64Bit() && in PerformDAGCombine()
6117 LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) { in PerformDAGCombine()
6131 DAG.getTargetConstant(CCVal, DL, Subtarget.getXLenVT()); in PerformDAGCombine()
6152 DAG.getTargetConstant(CCVal, DL, Subtarget.getXLenVT()); in PerformDAGCombine()
6172 LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) { in PerformDAGCombine()
6243 MVT XLenVT = Subtarget.getXLenVT(); in PerformDAGCombine()
6397 Subtarget.getFeatureBits(), in isDesirableToCommuteWithShift()
6400 ShiftedC1Int, Ty.getSizeInBits(), Subtarget.getFeatureBits(), in isDesirableToCommuteWithShift()
6458 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { in targetShrinkDemandedConstant()
6662 if (Op.getOperand(0).getScalarValueSizeInBits() > Subtarget.getXLen()) in ComputeNumSignBitsForTargetNode()
6664 return Subtarget.getXLen() - Op.getOperand(0).getScalarValueSizeInBits() + 1; in ComputeNumSignBitsForTargetNode()
6942 assert(!Subtarget.is64Bit() && in EmitInstrWithCustomInserter()
7304 if (Subtarget.hasStdExtV()) in analyzeInputArgs()
7335 if (Subtarget.hasStdExtV()) in analyzeOutputArgs()
7358 const RISCVSubtarget &Subtarget) { in convertLocVTToValVT() argument
7364 Val = convertFromScalableVector(VA.getValVT(), Val, DAG, Subtarget); in convertLocVTToValVT()
7400 const RISCVSubtarget &Subtarget) { in convertValVTToLocVT() argument
7408 Val = convertToScalableVector(LocVT, Val, DAG, Subtarget); in convertValVTToLocVT()
7673 MVT XLenVT = Subtarget.getXLenVT(); in LowerFormalArguments()
7674 unsigned XLenInBytes = Subtarget.getXLen() / 8; in LowerFormalArguments()
7848 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in isEligibleForTailCallOptimization()
7886 MVT XLenVT = Subtarget.getXLenVT(); in LowerCall()
8029 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL, Subtarget); in LowerCall()
8112 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in LowerCall()
8165 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL, Subtarget); in LowerCall()
8180 if (Subtarget.hasStdExtV()) in CanLowerReturn()
8251 Val = convertValVTToLocVT(DAG, Val, VA, DL, Subtarget); in LowerReturn()
8492 if (Subtarget.hasStdExtZfh() && VT == MVT::f16) in getRegForInlineAsmConstraint()
8494 if (Subtarget.hasStdExtF() && VT == MVT::f32) in getRegForInlineAsmConstraint()
8496 if (Subtarget.hasStdExtD() && VT == MVT::f64) in getRegForInlineAsmConstraint()
8560 if (Subtarget.hasStdExtF()) { in getRegForInlineAsmConstraint()
8597 if (Subtarget.hasStdExtD()) { in getRegForInlineAsmConstraint()
8606 if (Subtarget.hasStdExtV()) { in getRegForInlineAsmConstraint()
8686 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
8694 DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
8702 DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT())); in LowerAsmOperandForConstraint()
8807 unsigned XLen = Subtarget.getXLen(); in emitMaskedAtomicRMWIntrinsic()
8859 unsigned XLen = Subtarget.getXLen(); in emitMaskedAtomicCmpXchgIntrinsic()
8891 return Subtarget.hasStdExtZfh(); in isFMAFasterThanFMulAndFAdd()
8893 return Subtarget.hasStdExtF(); in isFMAFasterThanFMulAndFAdd()
8895 return Subtarget.hasStdExtD(); in isFMAFasterThanFMulAndFAdd()
8916 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in shouldExtendTypeInLibCall()
8924 if (Subtarget.is64Bit() && Type == MVT::i32) in shouldSignExtendTypeInLibCall()
8936 if (Subtarget.hasStdExtM() && VT.getSizeInBits() > Subtarget.getXLen()) in decomposeMulByConstant()
8946 if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) in decomposeMulByConstant()
9012 Val, DAG.getConstant(0, DL, Subtarget.getXLenVT())); in splitValueIntoRegisterParts()
9052 DAG.getConstant(0, DL, Subtarget.getXLenVT())); in joinRegisterPartsIntoValue()
9073 BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF); in getRegisterByName()
9074 if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg)) in getRegisterByName()