Lines Matching refs:Subtarget
145 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
152 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
161 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
186 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
216 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
232 if (Subtarget.useCRBits()) { in PPCTargetLowering()
235 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
309 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
344 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
349 if (Subtarget.hasVSX()) { in PPCTargetLowering()
354 if (Subtarget.hasFSQRT()) { in PPCTargetLowering()
359 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
382 if (Subtarget.hasSPE()) { in PPCTargetLowering()
390 if (Subtarget.hasSPE()) in PPCTargetLowering()
396 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
397 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
398 Subtarget.hasFRE())) in PPCTargetLowering()
401 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
402 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
403 Subtarget.hasFRES())) in PPCTargetLowering()
406 if (Subtarget.hasFCPSGN()) { in PPCTargetLowering()
414 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
430 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
434 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
442 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) { in PPCTargetLowering()
454 if (!Subtarget.useCRBits()) { in PPCTargetLowering()
467 if (!Subtarget.useCRBits()) in PPCTargetLowering()
470 if (Subtarget.hasFPU()) { in PPCTargetLowering()
481 if (!Subtarget.useCRBits()) in PPCTargetLowering()
486 if (Subtarget.hasSPE()) { in PPCTargetLowering()
510 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
567 if (Subtarget.is64BitELFABI()) { in PPCTargetLowering()
578 } else if (Subtarget.is32BitELFABI()) { in PPCTargetLowering()
586 if (Subtarget.is32BitELFABI()) in PPCTargetLowering()
614 if (Subtarget.hasSPE()) { in PPCTargetLowering()
636 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
651 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
657 if (Subtarget.hasSPE()) { in PPCTargetLowering()
667 if (Subtarget.hasFPCVT()) { in PPCTargetLowering()
668 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
689 if (Subtarget.use64BitRegs()) { in PPCTargetLowering()
707 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
714 if (Subtarget.hasVSX()) { in PPCTargetLowering()
721 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
750 if (Subtarget.hasVSX()) { in PPCTargetLowering()
756 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
766 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
839 if (!Subtarget.hasP8Vector()) { in PPCTargetLowering()
863 Subtarget.useCRBits() ? Legal : Expand); in PPCTargetLowering()
881 if (Subtarget.hasAltivec()) in PPCTargetLowering()
885 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
896 if (Subtarget.hasVSX()) { in PPCTargetLowering()
902 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
907 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
945 if (Subtarget.hasVSX()) { in PPCTargetLowering()
948 if (Subtarget.hasP8Vector()) { in PPCTargetLowering()
952 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1003 if (Subtarget.hasP8Vector()) in PPCTargetLowering()
1012 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1039 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1141 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1146 if (Subtarget.hasP9Vector()) { in PPCTargetLowering()
1203 } else if (Subtarget.hasVSX()) { in PPCTargetLowering()
1247 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1260 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1264 if (Subtarget.pairedVectorMemops()) { in PPCTargetLowering()
1269 if (Subtarget.hasMMA()) { in PPCTargetLowering()
1276 if (Subtarget.has64BitSupport()) in PPCTargetLowering()
1279 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1289 if (EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics()) in PPCTargetLowering()
1294 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
1320 if (Subtarget.hasFPCVT()) in PPCTargetLowering()
1325 if (Subtarget.useCRBits()) in PPCTargetLowering()
1340 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1346 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1377 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1384 switch (Subtarget.getCPUDirective()) { in PPCTargetLowering()
1406 if (Subtarget.enableMachineScheduler()) in PPCTargetLowering()
1415 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
1416 Subtarget.getCPUDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
1423 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { in PPCTargetLowering()
1441 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive(); in PPCTargetLowering()
1557 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
1558 if (Subtarget.hasAltivec()) in getByValTypeAlignment()
1564 return Subtarget.useSoftFloat(); in useSoftFloat()
1568 return Subtarget.hasSPE(); in hasSPE()
1737 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1846 const PPCSubtarget& Subtarget = in isVPKUDUMShuffleMask() local
1848 if (!Subtarget.hasP8Vector()) in isVPKUDUMShuffleMask()
2749 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2856 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
2955 if (isLoad && usePartialVectorLoads(N, Subtarget)) { in getPreIndexedAddressParts()
3017 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, in getLabelAccessInfo() argument
3060 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3063 : Subtarget.isAIXABI() in getTOCEntry()
3081 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerConstantPool()
3082 if (Subtarget.isUsingPCRelativeCalls()) { in LowerConstantPool()
3096 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerConstantPool()
3098 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerConstantPool()
3124 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3131 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3148 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3165 if (Subtarget.isUsingPCRelativeCalls()) { in LowerJumpTable()
3176 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerJumpTable()
3184 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerJumpTable()
3186 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerJumpTable()
3204 if (Subtarget.isUsingPCRelativeCalls()) { in LowerBlockAddress()
3215 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerBlockAddress()
3222 if (Subtarget.is32BitELFABI() && isPositionIndependent()) in LowerBlockAddress()
3229 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerBlockAddress()
3237 if (Subtarget.isAIXABI()) in LowerGlobalTLSAddress()
3283 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3291 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3312 bool IsPCRel = Subtarget.isUsingPCRelativeCalls(); in LowerGlobalTLSAddressLinux()
3344 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3368 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3408 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerGlobalAddress()
3409 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalAddress()
3432 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV); in LowerGlobalAddress()
3434 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerGlobalAddress()
3461 assert(!Subtarget.hasP9Vector() && in LowerSETCC()
3532 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3623 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3635 if (Subtarget.isAIXABI()) in LowerADJUST_TRAMPOLINE()
3694 if (Subtarget.isAIXABI()) in LowerINIT_TRAMPOLINE()
3738 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
3938 if (Subtarget.isAIXABI()) in LowerFormalArguments()
3941 if (Subtarget.is64BitELFABI()) in LowerFormalArguments()
3944 assert(Subtarget.is32BitELFABI()); in LowerFormalArguments()
3999 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_32SVR4()
4023 if (Subtarget.hasP8Vector()) in LowerFormalArguments_32SVR4()
4025 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4031 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
4033 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4056 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4062 if (!Subtarget.isLittleEndian()) in LowerFormalArguments_32SVR4()
4116 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_32SVR4()
4221 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerFormalArguments_64SVR4()
4222 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerFormalArguments_64SVR4()
4235 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_64SVR4()
4465 Subtarget.hasP8Vector() in LowerFormalArguments_64SVR4()
4469 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
4561 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_64SVR4()
4698 needStackSlotPassParameters(const PPCSubtarget &Subtarget, in needStackSlotPassParameters() argument
4700 assert(Subtarget.is64BitELFABI()); in needStackSlotPassParameters()
4703 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in needStackSlotPassParameters()
4823 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4835 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
4840 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
4857 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4859 else if (!CB && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4958 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in EmitTailCallStoreFPAndRetAddr() local
4959 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in EmitTailCallStoreFPAndRetAddr()
4960 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr()
4999 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5094 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerCallResult()
5105 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5115 if (!Subtarget.isLittleEndian()) in LowerCallResult()
5150 const PPCSubtarget &Subtarget, bool isPatchPoint) { in isIndirectCall() argument
5163 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() && in isIndirectCall()
5171 static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) { in isTOCSaveRestoreRequired() argument
5172 return Subtarget.isAIXABI() || in isTOCSaveRestoreRequired()
5173 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()); in isTOCSaveRestoreRequired()
5179 const PPCSubtarget &Subtarget, in getCallOpcode() argument
5194 return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC in getCallOpcode()
5198 if (Subtarget.isUsingPCRelativeCalls()) { in getCallOpcode()
5199 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."); in getCallOpcode()
5211 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) in getCallOpcode()
5219 const SDLoc &dl, const PPCSubtarget &Subtarget) { in transformCallee() argument
5220 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI()) in transformCallee()
5239 Subtarget.is32BitELFABI() && !isLocalCallee() && in transformCallee()
5240 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_; in transformCallee()
5243 const TargetMachine &TM = Subtarget.getTargetMachine(); in transformCallee()
5255 if (Subtarget.isAIXABI()) { in transformCallee()
5265 if (Subtarget.isAIXABI()) { in transformCallee()
5328 const PPCSubtarget &Subtarget) { in prepareDescriptorIndirectCall() argument
5357 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors() in prepareDescriptorIndirectCall()
5365 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister(); in prepareDescriptorIndirectCall()
5366 const MCRegister TOCReg = Subtarget.getTOCPointerRegister(); in prepareDescriptorIndirectCall()
5369 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset(); in prepareDescriptorIndirectCall()
5370 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset(); in prepareDescriptorIndirectCall()
5372 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5373 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4; in prepareDescriptorIndirectCall()
5402 assert((!hasNest || !Subtarget.isAIXABI()) && in prepareDescriptorIndirectCall()
5421 const PPCSubtarget &Subtarget) { in buildCallOperands() argument
5422 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5444 if (isTOCSaveRestoreRequired(Subtarget)) { in buildCallOperands()
5445 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in buildCallOperands()
5448 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in buildCallOperands()
5455 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest) in buildCallOperands()
5456 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), in buildCallOperands()
5478 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && in buildCallOperands()
5479 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) in buildCallOperands()
5480 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
5483 if (CFlags.IsVarArg && Subtarget.is32BitELFABI()) in buildCallOperands()
5487 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in buildCallOperands()
5505 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || in FinishCall()
5506 Subtarget.isAIXABI()) in FinishCall()
5511 Subtarget, DAG.getTarget()); in FinishCall()
5514 Callee = transformCallee(Callee, DAG, dl, Subtarget); in FinishCall()
5515 else if (Subtarget.usesFunctionDescriptors()) in FinishCall()
5517 dl, CFlags.HasNest, Subtarget); in FinishCall()
5524 SPDiff, Subtarget); in FinishCall()
5535 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && in FinishCall()
5585 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) in LowerCall()
5587 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
5604 assert((Subtarget.isUsingPCRelativeCalls() || in LowerCall()
5621 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) && in LowerCall()
5627 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint), in LowerCall()
5629 Subtarget.is64BitELFABI() && in LowerCall()
5633 if (Subtarget.isAIXABI()) in LowerCall()
5637 assert(Subtarget.isSVR4ABI()); in LowerCall()
5638 if (Subtarget.isPPC64()) in LowerCall()
5685 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(), in LowerCall_32SVR4()
5819 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
5820 bool IsLE = Subtarget.isLittleEndian(); in LowerCall_32SVR4()
5906 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerCall_64SVR4()
5907 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerCall_64SVR4()
5935 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_64SVR4()
6054 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_64SVR4()
6451 if (isTOCSaveRestoreRequired(Subtarget)) { in LowerCall_64SVR4()
6457 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_64SVR4()
6525 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( in CC_AIX() local
6527 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
6867 const PPCSubtarget &Subtarget = in LowerFormalArguments_AIX() local
6870 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
6882 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_AIX()
6943 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
6944 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7020 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in LowerFormalArguments_AIX()
7085 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7086 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7113 EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea); in LowerFormalArguments_AIX()
7173 const PPCSubtarget& Subtarget = in LowerCall_AIX() local
7185 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_AIX()
7186 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7448 const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister(); in LowerCall_AIX()
7449 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in LowerCall_AIX()
7450 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7452 Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_AIX()
7485 Outs, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in CanLowerReturn()
7500 (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerReturn()
7527 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7528 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerReturn()
7581 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE()
7602 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex()
7613 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); in getReturnAddrFrameIndex()
7625 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex()
7636 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); in getFramePointerFrameIndex()
7671 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA()
7813 if (Subtarget.isLittleEndian()) in LowerTRUNCATEVector()
7843 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
7853 Subtarget.hasSPE()) in LowerSELECT_CC()
7860 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
7986 const PPCSubtarget &Subtarget) { in convertFPToInt() argument
8015 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ); in convertFPToInt()
8018 assert((IsSigned || Subtarget.hasFPCVT()) && in convertFPToInt()
8035 SDValue Tmp = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTForReuse()
8041 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8042 (IsSigned || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
8067 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4); in LowerFP_TO_INTForReuse()
8082 SDValue Conv = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTDirectMove()
8101 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerFP_TO_INT()
8182 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8210 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8286 if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2) in directMoveIsProfitable()
8308 const PPCSubtarget &Subtarget, in convertIntToFP() argument
8320 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8342 assert(Subtarget.hasFPCVT() && in LowerINT_TO_FPDirectMove()
8350 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
8402 if (Subtarget.isLittleEndian()) in LowerINT_TO_FPVector()
8417 if (Subtarget.hasP9Altivec()) in LowerINT_TO_FPVector()
8454 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerINT_TO_FP()
8472 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) && in LowerINT_TO_FP()
8473 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8476 assert((IsSigned || Subtarget.hasFPCVT()) && in LowerINT_TO_FP()
8492 !Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8537 } else if (Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8547 } else if (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8557 } else if (((Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8559 (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8594 SDValue FP = convertIntToFP(Op, Bits, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8598 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8621 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8654 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
8676 SDValue FP = convertIntToFP(Op, Ld, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8679 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9086 HasAnyUndefs, 0, !Subtarget.isLittleEndian()); in LowerBUILD_VECTOR()
9093 Subtarget.hasPrefixInstrs()) { in LowerBUILD_VECTOR()
9153 ((Subtarget.hasVSX() && ElementSize == 64) || in LowerBUILD_VECTOR()
9154 (Subtarget.hasP9Vector() && ElementSize == 32))) { in LowerBUILD_VECTOR()
9174 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
9175 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove(), in LowerBUILD_VECTOR()
9176 Subtarget.hasP8Vector())) in LowerBUILD_VECTOR()
9202 if (Subtarget.hasPrefixInstrs() && SplatSize == 2) in LowerBUILD_VECTOR()
9206 if (Subtarget.hasPrefixInstrs() && SplatSize == 4) in LowerBUILD_VECTOR()
9211 if (Subtarget.hasP9Vector() && SplatSize == 1) in LowerBUILD_VECTOR()
9314 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR()
9320 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR()
9326 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR()
9417 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTB()
9523 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTH()
9659 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) || in lowerToXXSPLTI32DX()
9671 bool IsLE = Subtarget.isLittleEndian(); in lowerToXXSPLTI32DX()
9748 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVECTOR_SHUFFLE()
9758 if (InputLoad && Subtarget.hasVSX() && V2.isUndef() && in LowerVECTOR_SHUFFLE()
9778 if ((IsFourByte && Subtarget.hasP9Vector()) || !IsFourByte) { in LowerVECTOR_SHUFFLE()
9810 if (Subtarget.hasP9Vector() && in LowerVECTOR_SHUFFLE()
9829 if (Subtarget.hasPrefixInstrs()) { in LowerVECTOR_SHUFFLE()
9835 if (Subtarget.hasP9Altivec()) { in LowerVECTOR_SHUFFLE()
9844 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
9857 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
9870 if (Subtarget.hasP9Vector()) { in LowerVECTOR_SHUFFLE()
9890 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
9924 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
9945 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10053 bool &isDot, const PPCSubtarget &Subtarget) { in getVectorCompareInfo() argument
10083 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10095 if (Subtarget.hasP9Altivec()) { in getVectorCompareInfo()
10143 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10162 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10172 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10196 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
10239 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10250 if (Subtarget.hasP9Altivec()) in getVectorCompareInfo()
10292 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10307 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10315 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10348 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10364 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10377 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) in LowerINTRINSIC_WO_CHAIN()
10445 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); in LowerINTRINSIC_VOID()
10461 if (!Subtarget.isPPC64()) in LowerBSWAP()
10470 if (Subtarget.isLittleEndian()) in LowerBSWAP()
10545 if (Subtarget.isISA3_1()) { in LowerINSERT_VECTOR_ELT()
10546 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
10574 if (Subtarget.isLittleEndian()) { in LowerINSERT_VECTOR_ELT()
10597 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
10599 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
10616 if (Subtarget.isLittleEndian()) { in LowerVectorLoad()
10643 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
10645 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
10655 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
10700 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerMUL()
10738 !Subtarget.hasP9Vector()) in LowerFP_ROUND()
10780 if (Subtarget.isLittleEndian()) in LowerFP_EXTEND()
10941 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
11016 if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) in emitTrailingFence()
11035 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitAtomicBinary()
11045 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
11050 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
11207 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in EmitPartwordAtomicBinary()
11225 if (Subtarget.hasPartwordAtomics()) in EmitPartwordAtomicBinary()
11233 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
11234 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitPartwordAtomicBinary()
11420 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjSetJmp()
11421 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo(); in emitEHSjLjSetJmp()
11488 if (Subtarget.is64BitELFABI()) { in emitEHSjLjSetJmp()
11501 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
11503 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
11506 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
11529 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
11532 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
11562 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjLongJmp()
11580 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29 in emitEHSjLjLongJmp()
11643 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
11669 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); in getStackProbeSize()
11695 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca()
11697 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitProbedAlloca()
11859 if (Subtarget.is64BitELFABI() && in EmitInstrWithCustomInserter()
11861 !Subtarget.isUsingPCRelativeCalls()) { in EmitInstrWithCustomInserter()
11881 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitInstrWithCustomInserter()
12133 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12135 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12147 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
12152 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
12238 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
12239 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitInstrWithCustomInserter()
12522 if (Subtarget.hasDirectMove()) { in EmitInstrWithCustomInserter()
12662 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { in getEstimateRefinementSteps() argument
12667 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3; in getEstimateRefinementSteps()
12679 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
12708 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
12719 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
12720 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
12721 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
12722 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
12724 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getSqrtEstimate()
12728 UseOneConstNR = !Subtarget.needsTwoConstNR(); in getSqrtEstimate()
12738 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
12739 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
12740 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
12741 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
12743 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getRecipEstimate()
12760 switch (Subtarget.getCPUDirective()) { in combineRepeatedFPDivisors()
13049 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits"); in DAGCombineTruncBoolExt()
13349 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
13350 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
14012 if (!Subtarget.hasVSX()) in DAGCombineBuildVector()
14035 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
14044 if (Subtarget.isISA3_1()) { in DAGCombineBuildVector()
14082 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0; in DAGCombineBuildVector()
14084 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1; in DAGCombineBuildVector()
14101 if (useSoftFloat() || !Subtarget.has64BitSupport()) in combineFPToIntToFP()
14122 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) { in combineFPToIntToFP()
14154 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in combineFPToIntToFP()
14159 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14164 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14171 Subtarget.hasFPCVT()) || in combineFPToIntToFP()
14189 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
14241 if (Subtarget.needsSwapsForVSXMemOps() && MMO->getAlign() >= Align(16) && in expandVSXLoadForLE()
14312 if (Subtarget.needsSwapsForVSXMemOps() && MMO->getAlign() >= Align(16) && in expandVSXStoreForLE()
14356 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14358 if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) in combineStoreFPToInt()
14361 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || in combineStoreFPToInt()
14451 const PPCSubtarget &Subtarget) { in fixupShuffleMaskForPermutedSToV() argument
14456 Subtarget.isLittleEndian() ? HalfVec : HalfVec - ValidLaneWidth; in fixupShuffleMaskForPermutedSToV()
14466 const PPCSubtarget &Subtarget) { in getSToVPermuted() argument
14486 ResultInElt -= Subtarget.isLittleEndian() ? 0 : 1; in getSToVPermuted()
14515 bool IsLittleEndian = Subtarget.isLittleEndian(); in combineVectorShuffle()
14522 if (!Subtarget.hasDirectMove()) in combineVectorShuffle()
14573 SToVLHS = getSToVPermuted(SToVLHS, DAG, Subtarget); in combineVectorShuffle()
14583 SToVRHS = getSToVPermuted(SToVRHS, DAG, Subtarget); in combineVectorShuffle()
14595 HalfVec, ValidLaneWidth, Subtarget); in combineVectorShuffle()
14681 if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX()) in combineVReverseMemOP()
14687 if (!Subtarget.hasP9Vector()) in combineVReverseMemOP()
14804 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
14839 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
14860 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
14875 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
14941 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
14990 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && in PerformDAGCombine()
14992 !Subtarget.hasP8Vector() && in PerformDAGCombine()
14999 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
15104 Perm = Subtarget.hasAltivec() in PerformDAGCombine()
15119 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
15171 if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && in PerformDAGCombine()
15207 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
15220 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
15235 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
15240 (Subtarget.hasLDBRX() && Is64BitBswapOn64BitTgt))) { in PerformDAGCombine()
15292 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
15415 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) { in PerformDAGCombine()
15482 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
15554 switch (Subtarget.getCPUDirective()) { in getPrefLoopAlignment()
15579 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in getPrefLoopAlignment()
15701 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
15705 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
15713 if (Subtarget.hasSPE()) { in getRegForInlineAsmConstraint()
15726 if (Subtarget.hasAltivec()) in getRegForInlineAsmConstraint()
15732 } else if (Constraint == "wc" && Subtarget.useCRBits()) { in getRegForInlineAsmConstraint()
15737 Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
15742 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
15745 } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
15746 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
15779 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
15783 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
15798 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
15811 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) { in getRegForInlineAsmConstraint()
15910 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
15959 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR()
15965 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl, in LowerRETURNADDR()
16010 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName()
16029 if (Subtarget.is32BitELFABI()) in isAccessedAsGotIndirect()
16034 if (Subtarget.isAIXABI()) in isAccessedAsGotIndirect()
16048 return Subtarget.isGVIndirectSymbol(G->getGlobal()); in isAccessedAsGotIndirect()
16174 if (Subtarget.hasAltivec() && Op.size() >= 16 && in getOptimalMemOpType()
16176 ((Op.isMemset() && Subtarget.hasVSX()) || Subtarget.hasP8Vector()))) in getOptimalMemOpType()
16180 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
16219 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
16266 !Subtarget.allowsUnalignedFPAccess()) in allowsMisalignedMemoryAccesses()
16270 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
16328 return Subtarget.hasP9Vector(); in isFMAFasterThanFMulAndFAdd()
16401 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
16406 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
16413 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves in shouldExpandBuildVectorWithShuffles()
16415 if (Subtarget.hasVSX()) in shouldExpandBuildVectorWithShuffles()
16422 if (DisableILPPref || Subtarget.enableMachineScheduler()) in getSchedulingPreference()
16515 if (!Subtarget.isTargetLinux()) in useLoadStackGuardNode()
16523 if (Subtarget.isAIXABI()) { in insertSSPDeclarations()
16528 if (!Subtarget.isTargetLinux()) in insertSSPDeclarations()
16533 if (Subtarget.isAIXABI()) in getSDagStackGuard()
16540 if (!VT.isSimple() || !Subtarget.hasVSX()) in isFPImmLegal()
16550 if (Subtarget.hasPrefixInstrs()) { in isFPImmLegal()
16600 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
16643 const PPCSubtarget &Subtarget) { in combineADDToADDZE() argument
16644 if (!Subtarget.isPPC64()) in combineADDToADDZE()
16729 const PPCSubtarget &Subtarget) { in combineADDToMAT_PCREL_ADDR() argument
16730 if (!Subtarget.isUsingPCRelativeCalls()) in combineADDToMAT_PCREL_ADDR()
16770 if (auto Value = combineADDToADDZE(N, DCI.DAG, Subtarget)) in combineADD()
16773 if (auto Value = combineADDToMAT_PCREL_ADDR(N, DCI.DAG, Subtarget)) in combineADD()
16791 if (Subtarget.useCRBits()) { in combineTRUNCATE()
16801 if (Subtarget.hasP9Altivec() && Op0.getOpcode() == ISD::ABS) { in combineTRUNCATE()
16862 switch (this->Subtarget.getCPUDirective()) { in combineMUL()
16973 if (!Subtarget.is64BitELFABI()) in mayBeEmittedAsTailCall()
17002 if (!Subtarget.hasVSX()) in hasBitPreservingFPLogic()
17004 if (Subtarget.hasP9Vector() && VT == MVT::f128) in hasBitPreservingFPLogic()
17034 assert(Subtarget.hasP9Altivec() && in combineABS()
17078 assert(Subtarget.hasP9Altivec() && in combineVSelect()
17246 if (!Subtarget.hasP9Vector()) in computeMOFlags()
17250 if (Subtarget.hasPrefixInstrs()) in computeMOFlags()
17253 if (Subtarget.hasSPE()) in computeMOFlags()
17361 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
17444 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
17476 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
17499 if (EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && Size == 128) in shouldExpandAtomicRMWInIR()
17510 if (EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && Size == 128) in shouldExpandAtomicCmpXchgInIR()
17540 assert(EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && in emitMaskedAtomicRMWIntrinsic()
17565 assert(EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics() && in emitMaskedAtomicCmpXchgIntrinsic()