| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 48 Register Addr;
49 Register Base;
50 Register Offset;
56 Register Base;
60 Register Reg;
353 std::pair<Register, Register> &MatchInfo);
355 std::pair<Register, Register> &MatchInfo);
427 std::tuple<Register, Register> &MatchInfo);
568 bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
571 bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
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| H A D | Utils.h | 85 Register constrainRegToClass(MachineRegisterInfo &MRI,
141 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
165 Optional<APInt> getConstantVRegVal(Register VReg,
177 Register VReg;
195 const ConstantFP* getConstantFPVRegVal(Register VReg,
208 Register Reg;
222 MachineInstr *getDefIgnoringCopies(Register Reg,
231 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
251 const Register Op2,
323 Register Reg;
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| H A D | CallLowering.h | 261 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
267 virtual void assignValueToAddress(Register ValVReg, Register Addr,
295 copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
302 Register extendRegister(Register ValReg, CCValAssign &VA,
314 Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
317 void assignValueToReg(Register ValVReg, Register PhysReg,
390 Register ThisReturnReg = Register()) const;
399 Register ThisReturnReg = Register()) const;
439 ArrayRef<Register> VRegs, Register DemoteReg,
445 ArrayRef<Register> VRegs, Register DemoteReg) const;
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| H A D | GISelKnownBits.h | 36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
78 bool maskedValueIsZero(Register Val, const APInt &Mask) { in maskedValueIsZero()
84 bool signBitIsZero(Register Op);
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| H A D | LegalizationArtifactCombiner.h | 63 Register TruncSrc; in tryCombineAnyExt()
73 Register ExtSrc; in tryCombineAnyExt()
113 Register TruncSrc; in tryCombineZExt()
114 Register SextSrc; in tryCombineZExt()
134 Register ZextSrc; in tryCombineZExt()
171 Register TruncSrc; in tryCombineSExt()
188 Register ExtSrc; in tryCombineSExt()
502 static void replaceRegOrBuildCopy(Register DstReg, Register SrcReg, in replaceRegOrBuildCopy()
708 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef()
1245 Register lookThroughCopyInstrs(Register Reg) { in lookThroughCopyInstrs()
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| H A D | LegalizerHelper.h | 120 Register coerceToScalar(Register Val);
165 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
186 void extractParts(Register Reg, LLT Ty, int NumParts,
187 SmallVectorImpl<Register> &VRegs);
190 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
192 SmallVectorImpl<Register> &VRegs,
204 void insertParts(Register DstReg, LLT ResultTy,
213 LLT NarrowTy, Register SrcReg);
219 Register SrcReg);
250 ArrayRef<Register> Src1Regs,
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 101 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
598 void replaceRegWith(Register FromReg, Register ToReg);
709 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
728 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
774 void addRegAllocationHint(Register VReg, Register PrefReg) { in addRegAllocationHint()
781 void setSimpleHint(Register VReg, Register PrefReg) { in setSimpleHint()
794 std::pair<Register, Register>
805 Register getSimpleHint(Register VReg) const { in getSimpleHint()
807 std::pair<Register, Register> Hint = getRegAllocationHint(VReg); in getSimpleHint()
813 const std::pair<Register, SmallVector<Register, 4>>
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| H A D | VirtRegMap.h | 100 bool hasPhys(Register virtReg) const { in hasPhys()
106 MCRegister getPhys(Register virtReg) const { in getPhys()
117 bool hasShape(Register virtReg) const { in hasShape()
121 ShapeT getShape(Register virtReg) const { in getShape()
132 void clearVirt(Register virtReg) { in clearVirt()
154 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg()
162 Register getPreSplitReg(Register virtReg) const { in getPreSplitReg()
170 Register getOriginal(Register VirtReg) const { in getOriginal()
171 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
188 int getStackSlot(Register virtReg) const { in getStackSlot()
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| H A D | FunctionLoweringInfo.h | 70 Register DemoteRegister;
78 DenseMap<const Value *, Register> ValueMap;
85 DenseMap<Register, const Value*> VirtReg2Value;
89 const Value *getValueFromVirtualReg(Register Vreg);
111 Register Reg;
139 DenseMap<Register, Register> RegFixups;
141 DenseSet<Register> RegsWithFixups;
201 Register CreateRegs(const Value *V);
205 Register InitializeRegForValue(const Value *V) { in InitializeRegForValue()
209 Register &R = ValueMap[V]; in InitializeRegForValue()
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| H A D | LiveVariables.h | 108 bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
156 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
163 MachineInstr *FindLastRefOrPartRef(Register Reg);
168 MachineInstr *FindLastPartialDef(Register Reg,
272 VarInfo &getVarInfo(Register Reg);
280 void HandleVirtRegDef(Register reg, MachineInstr &MI);
283 bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) { in isLiveIn()
290 bool isLiveOut(Register Reg, const MachineBasicBlock &MBB);
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| H A D | Register.h | 19 class Register {
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register() function
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index()
58 static Register index2StackSlot(int FI) { in index2StackSlot()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
77 static unsigned virtReg2Index(Register Reg) { in virtReg2Index()
84 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
148 template<> struct DenseMapInfo<Register> {
155 static unsigned getHashValue(const Register &Val) {
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| H A D | LiveRangeEdit.h | 60 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
63 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
67 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
72 SmallVectorImpl<Register> &NewRegs;
113 void MRI_NoteNewVirtualRegister(Register VReg) override;
151 Register getReg() const { return getParent().reg(); } in getReg()
154 using iterator = SmallVectorImpl<Register>::const_iterator;
171 ArrayRef<Register> regs() const { in regs()
176 Register createFrom(Register OldReg);
184 Register create() { return createFrom(getReg()); } in create()
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| H A D | TailDuplicator.h | 53 SmallVector<Register, 16> SSAUpdateVRs;
57 using AvailableValsTy = std::vector<std::pair<MachineBasicBlock *, Register>>;
59 DenseMap<Register, AvailableValsTy> SSAUpdateVals;
101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
105 DenseMap<Register, RegSubRegPair> &LocalVRMap,
106 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies,
107 const DenseSet<Register> &UsedByPhi, bool Remove);
110 DenseMap<Register, RegSubRegPair> &LocalVRMap,
111 const DenseSet<Register> &UsedByPhi);
118 const DenseSet<Register> &RegsUsedByPhi,
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| H A D | FastISel.h | 90 Register ResultReg;
95 SmallVector<Register, 16> OutRegs;
97 SmallVector<Register, 4> InRegs;
201 DenseMap<const Value *, Register> LocalValueMap;
268 Register getRegForValue(const Value *V);
273 Register lookUpRegForValue(const Value *V);
277 Register getRegForGEPIndex(const Value *Idx);
383 Register fastEmitInst_(unsigned MachineInstOpcode,
388 Register fastEmitInst_r(unsigned MachineInstOpcode,
438 Register fastEmitZExtFromI1(MVT VT, unsigned Op0);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 49 Register SrcReg,
50 DenseMap<SDValue, Register> &VRBaseMap);
56 DenseMap<SDValue, Register> &VRBaseMap);
60 Register getVR(SDValue Op,
61 DenseMap<SDValue, Register> &VRBaseMap);
70 DenseMap<SDValue, Register> &VRBaseMap,
81 DenseMap<SDValue, Register> &VRBaseMap,
87 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
141 DenseMap<SDValue, Register> &VRBaseMap) { in EmitNode()
161 DenseMap<SDValue, Register> &VRBaseMap);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineSSAUpdater.cpp | 63 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
89 return Register(); in LookForIdenticalPHI()
93 return Register(); in LookForIdenticalPHI()
101 Register SrcReg = I->getOperand(i).getReg(); in LookForIdenticalPHI()
112 return Register(); in LookForIdenticalPHI()
124 Register NewVR = MRI->createVirtualRegister(RC); in InsertNewDef()
164 Register SingularValue; in GetValueInMiddleOfBlock()
176 SingularValue = Register(); in GetValueInMiddleOfBlock()
226 Register NewVR; in RewriteUse()
245 using ValT = Register;
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| H A D | MachineRegisterInfo.cpp | 63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
147 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
157 Register
172 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister()
187 Register
205 Register Reg = Register::index2VirtReg(i); in clearVirtRegs()
258 verifyUseList(Register::index2VirtReg(i)); in verifyUseLists()
380 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { in replaceRegWith()
389 if (Register::isPhysicalRegister(ToReg)) { in replaceRegWith()
458 return Register(); in getLiveInVirtReg()
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| H A D | TwoAddressInstructionPass.cpp | 114 DenseMap<Register, Register> SrcRegMap;
119 DenseMap<Register, Register> DstRegMap;
121 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131 bool isProfitableToConv3Addr(Register RegA, Register RegB);
386 Register SrcReg; in findOnlyInterestingUse()
405 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
416 static bool regsAreCompatible(Register RegA, Register RegB, in regsAreCompatible()
592 Register RegA, Register RegB, unsigned Dist) { in convertInstTo3Addr()
643 Register NewReg; in scanUses()
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| H A D | RegAllocFast.cpp | 285 Register traceCopies(Register VirtReg) const;
286 Register traceCopyChain(Register Reg) const;
691 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
706 Register RegAllocFast::traceCopyChain(Register Reg) const { in traceCopyChain()
725 Register RegAllocFast::traceCopies(Register VirtReg) const { in traceCopies()
739 return Register(); in traceCopies()
767 Hint0 = Register(); in allocVirtReg()
786 Hint1 = Register(); in allocVirtReg()
835 Register VirtReg = MO.getReg(); in allocVirtRegUndef()
966 Register Hint; in useVirtReg()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 312 Register UndefReg; in matchCombineShuffleVector()
721 Register LoadReg; in applySextInRegOfLoad()
2036 static Register peekThroughBitcast(Register Reg, in peekThroughBitcast()
2575 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in matchCombineTruncOfShl() argument
2599 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in applyCombineTruncOfShl() argument
3025 Register Src; in matchAshrShlToSextInreg()
3042 Register Src; in applyAshShlToSextInreg()
3059 Register R; in matchOverlappingAnd()
3304 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in matchXorOfAndWithSameReg() argument
3335 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in applyXorOfAndWithSameReg() argument
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| H A D | LegalizerHelper.cpp | 276 Register PadReg; in buildLCMMergePieces()
304 Register AllPadReg; in buildLCMMergePieces()
1316 Register LegalizerHelper::coerceToScalar(Register Val) { in coerceToScalar()
1848 Register NewOp; in widenScalarAddSubOverflow()
4467 Register Hi, Lo; in fewerElementsVectorShuffle()
4688 Register Res = in tryNarrowPow2Reduction()
4719 SrcOp Lo(Register(0)), Hi(Register(0)); in narrowScalarShiftByConstant()
5972 Register ShVal; in lowerRotate()
6428 Register And1; in lowerFCopySign()
6710 Register Val; in lowerShuffleVector()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.h | 41 Register getSegmentAperture(unsigned AddrSpace,
93 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
96 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
106 Register DstRemReg, Register Num,
107 Register Den) const;
110 Register DstRemReg, Register Numer,
111 Register Denom) const;
137 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI,
147 void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
148 Register SOffset, unsigned ImmOffset, Register VIndex,
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| H A D | SIMachineFunctionInfo.h | 338 Register TIDReg = AMDGPU::NoRegister;
442 Register VGPR;
454 Register VGPR;
494 Register SGPRForFPSaveRestoreCopy;
499 Register SGPRForBPSaveRestoreCopy;
502 Register VGPRReservedForSGPRSpill;
579 Register addWorkGroupIDX() {
585 Register addWorkGroupIDY() {
591 Register addWorkGroupIDZ() {
597 Register addWorkGroupInfo() {
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| H A D | AMDGPURegisterBankInfo.h | 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
59 SmallSet<Register, 4> &SGPROperandRegs,
87 Register Reg) const;
89 std::pair<Register, unsigned>
90 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
99 Register Ptr) const;
108 const ValueMapping *getSGPROpMapping(Register Reg,
113 const ValueMapping *getVGPROpMapping(Register Reg,
118 const ValueMapping *getAGPROpMapping(Register Reg,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZMachineFunctionInfo.h | 32 Register VarArgsFirstGPR;
33 Register VarArgsFirstFPR;
50 void setSpillGPRRegs(Register Low, Register High, unsigned Offs) { in setSpillGPRRegs()
60 void setRestoreGPRRegs(Register Low, Register High, unsigned Offs) { in setRestoreGPRRegs()
68 Register getVarArgsFirstGPR() const { return VarArgsFirstGPR; } in getVarArgsFirstGPR()
69 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
72 Register getVarArgsFirstFPR() const { return VarArgsFirstFPR; } in getVarArgsFirstFPR()
73 void setVarArgsFirstFPR(Register FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR()
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