Lines Matching refs:Register
123 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith()
124 Register ToReg) const { in replaceRegWith()
137 Register ToReg) const { in replaceRegOpWith()
156 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
157 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
161 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
162 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
169 SmallVector<Register, 4> Ops; in tryCombineConcatVectors()
178 SmallVectorImpl<Register> &Ops) { in matchCombineConcatVectors()
188 Register Reg = MO.getReg(); in matchCombineConcatVectors()
223 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) { in applyCombineConcatVectors()
226 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
228 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineConcatVectors()
245 SmallVector<Register, 4> Ops; in tryCombineShuffleVector()
254 SmallVectorImpl<Register> &Ops) { in matchCombineShuffleVector()
258 Register Src1 = MI.getOperand(1).getReg(); in matchCombineShuffleVector()
312 Register UndefReg; in matchCombineShuffleVector()
313 Register Src2 = MI.getOperand(2).getReg(); in matchCombineShuffleVector()
330 const ArrayRef<Register> Ops) { in applyCombineShuffleVector()
331 Register DstReg = MI.getOperand(0).getReg(); in applyCombineShuffleVector()
333 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineShuffleVector()
450 Register LoadReg = LoadMI->getDstReg(); in matchCombineExtendingLoads()
519 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg(); in applyCombineExtendingLoads()
536 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg()); in applyCombineExtendingLoads()
563 Register UseDstReg = UseMI->getOperand(0).getReg(); in applyCombineExtendingLoads()
656 Register SrcReg = MI.getOperand(1).getReg(); in matchSextTruncSextLoad()
657 Register LoadUser = SrcReg; in matchSextTruncSextLoad()
662 Register TruncSrc; in matchSextTruncSextLoad()
688 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchSextInRegOfLoad() argument
695 Register SrcReg = MI.getOperand(1).getReg(); in matchSextInRegOfLoad()
719 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applySextInRegOfLoad() argument
721 Register LoadReg; in applySextInRegOfLoad()
742 bool CombinerHelper::findPostIndexCandidate(MachineInstr &MI, Register &Addr, in findPostIndexCandidate()
743 Register &Base, Register &Offset) { in findPostIndexCandidate()
810 bool CombinerHelper::findPreIndexCandidate(MachineInstr &MI, Register &Addr, in findPreIndexCandidate()
811 Register &Base, Register &Offset) { in findPreIndexCandidate()
965 Register Src1 = MI.getOperand(1).getReg(); in matchCombineDivRem()
1010 Register DestDivReg, DestRemReg; in applyCombineDivRem()
1179 static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) { in getMemsetValue()
1211 bool CombinerHelper::optimizeMemset(MachineInstr &MI, Register Dst, in optimizeMemset()
1212 Register Val, uint64_t KnownLen, in optimizeMemset()
1270 Register MemSetValue = getMemsetValue(Val, LargestTy, MIB); in optimizeMemset()
1292 Register Value = MemSetValue; in optimizeMemset()
1308 Register Ptr = Dst; in optimizeMemset()
1327 Register Dst = MI.getOperand(0).getReg(); in tryEmitMemcpyInline()
1328 Register Src = MI.getOperand(1).getReg(); in tryEmitMemcpyInline()
1329 Register Len = MI.getOperand(2).getReg(); in tryEmitMemcpyInline()
1355 bool CombinerHelper::tryEmitMemcpyInline(MachineInstr &MI, Register Dst, in tryEmitMemcpyInline()
1356 Register Src, uint64_t KnownLen, in tryEmitMemcpyInline()
1365 bool CombinerHelper::optimizeMemcpy(MachineInstr &MI, Register Dst, in optimizeMemcpy()
1366 Register Src, uint64_t KnownLen, in optimizeMemcpy()
1448 Register LoadPtr = Src; in optimizeMemcpy()
1449 Register Offset; in optimizeMemcpy()
1458 Register StorePtr = in optimizeMemcpy()
1469 bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst, in optimizeMemmove()
1470 Register Src, uint64_t KnownLen, in optimizeMemmove()
1537 SmallVector<Register, 16> LoadVals; in optimizeMemmove()
1544 Register LoadPtr = Src; in optimizeMemmove()
1561 Register StorePtr = Dst; in optimizeMemmove()
1586 Register Dst = MI.getOperand(0).getReg(); in tryCombineMemCpyFamily()
1587 Register Src = MI.getOperand(1).getReg(); in tryCombineMemCpyFamily()
1588 Register Len = MI.getOperand(2).getReg(); in tryCombineMemCpyFamily()
1635 const Register Op, in constantFoldFpUnary()
1678 Register DstReg = MI.getOperand(0).getReg(); in matchCombineConstantFoldFpUnary()
1679 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineConstantFoldFpUnary()
1691 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConstantFoldFpUnary()
1707 Register Add2 = MI.getOperand(1).getReg(); in matchPtrAddImmedChain()
1708 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain()
1724 Register Base = Add2Def->getOperand(1).getReg(); in matchPtrAddImmedChain()
1725 Register Imm2 = Add2Def->getOperand(2).getReg(); in matchPtrAddImmedChain()
1763 Register Shl2 = MI.getOperand(1).getReg(); in matchShiftImmedChain()
1764 Register Imm1 = MI.getOperand(2).getReg(); in matchShiftImmedChain()
1773 Register Base = Shl2Def->getOperand(1).getReg(); in matchShiftImmedChain()
1774 Register Imm2 = Shl2Def->getOperand(2).getReg(); in matchShiftImmedChain()
1819 Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); in applyShiftImmedChain()
1847 Register LogicDest = MI.getOperand(1).getReg(); in matchShiftOfShiftedLogic()
1858 const Register C1 = MI.getOperand(2).getReg(); in matchShiftOfShiftedLogic()
1882 Register LogicMIReg1 = LogicMI->getOperand(1).getReg(); in matchShiftOfShiftedLogic()
1884 Register LogicMIReg2 = LogicMI->getOperand(2).getReg(); in matchShiftOfShiftedLogic()
1919 Register Const = Builder.buildConstant(ShlType, MatchInfo.ValSum).getReg(0); in applyShiftOfShiftedLogic()
1921 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
1922 Register Shift1 = in applyShiftOfShiftedLogic()
1925 Register Shift2Const = MI.getOperand(2).getReg(); in applyShiftOfShiftedLogic()
1926 Register Shift2 = Builder in applyShiftOfShiftedLogic()
1931 Register Dest = MI.getOperand(0).getReg(); in applyShiftOfShiftedLogic()
1970 Register LHS = MI.getOperand(1).getReg(); in matchCombineShlOfExtend()
1972 Register ExtSrc; in matchCombineShlOfExtend()
1979 Register RHS = MI.getOperand(2).getReg(); in matchCombineShlOfExtend()
2005 Register ExtSrcReg = MatchData.Reg; in applyCombineShlOfExtend()
2018 Register &MatchInfo) { in matchCombineMergeUnmerge()
2020 SmallVector<Register, 16> MergedValues; in matchCombineMergeUnmerge()
2036 static Register peekThroughBitcast(Register Reg, in peekThroughBitcast()
2045 MachineInstr &MI, SmallVectorImpl<Register> &Operands) { in matchCombineUnmergeMergeToPlainValues()
2048 Register SrcReg = in matchCombineUnmergeMergeToPlainValues()
2072 MachineInstr &MI, SmallVectorImpl<Register> &Operands) { in applyCombineUnmergeMergeToPlainValues()
2084 Register DstReg = MI.getOperand(Idx).getReg(); in applyCombineUnmergeMergeToPlainValues()
2085 Register SrcReg = Operands[Idx]; in applyCombineUnmergeMergeToPlainValues()
2097 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in matchCombineUnmergeConstant()
2128 Register DstReg = MI.getOperand(Idx).getReg(); in applyCombineUnmergeConstant()
2148 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc()
2157 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc()
2170 Register Dst0Reg = MI.getOperand(0).getReg(); in matchCombineUnmergeZExtToZExt()
2177 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in matchCombineUnmergeZExtToZExt()
2182 Register ZExtSrcReg; in matchCombineUnmergeZExtToZExt()
2197 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeZExtToZExt()
2204 Register ZExtSrcReg = ZExtInstr->getOperand(1).getReg(); in applyCombineUnmergeZExtToZExt()
2218 Register ZeroReg; in applyCombineUnmergeZExtToZExt()
2254 Register DstReg = MI.getOperand(0).getReg(); in applyCombineShiftToUnmerge()
2255 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineShiftToUnmerge()
2268 Register Narrowed = Unmerge.getReg(1); in applyCombineShiftToUnmerge()
2283 Register Narrowed = Unmerge.getReg(0); in applyCombineShiftToUnmerge()
2336 bool CombinerHelper::matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) { in matchCombineI2PToP2I()
2338 Register DstReg = MI.getOperand(0).getReg(); in matchCombineI2PToP2I()
2340 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineI2PToP2I()
2345 void CombinerHelper::applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) { in applyCombineI2PToP2I()
2347 Register DstReg = MI.getOperand(0).getReg(); in applyCombineI2PToP2I()
2353 bool CombinerHelper::matchCombineP2IToI2P(MachineInstr &MI, Register &Reg) { in matchCombineP2IToI2P()
2355 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineP2IToI2P()
2359 void CombinerHelper::applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) { in applyCombineP2IToI2P()
2361 Register DstReg = MI.getOperand(0).getReg(); in applyCombineP2IToI2P()
2368 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2370 Register LHS = MI.getOperand(1).getReg(); in matchCombineAddP2IToPtrAdd()
2371 Register RHS = MI.getOperand(2).getReg(); in matchCombineAddP2IToPtrAdd()
2377 for (Register SrcReg : {LHS, RHS}) { in matchCombineAddP2IToPtrAdd()
2393 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2394 Register Dst = MI.getOperand(0).getReg(); in applyCombineAddP2IToPtrAdd()
2395 Register LHS = MI.getOperand(1).getReg(); in applyCombineAddP2IToPtrAdd()
2396 Register RHS = MI.getOperand(2).getReg(); in applyCombineAddP2IToPtrAdd()
2414 Register LHS = MI.getOperand(1).getReg(); in matchCombineConstPtrAddToI2P()
2415 Register RHS = MI.getOperand(2).getReg(); in matchCombineConstPtrAddToI2P()
2432 Register Dst = MI.getOperand(0).getReg(); in applyCombineConstPtrAddToI2P()
2439 bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) { in matchCombineAnyExtTrunc()
2441 Register DstReg = MI.getOperand(0).getReg(); in matchCombineAnyExtTrunc()
2442 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineAnyExtTrunc()
2448 bool CombinerHelper::matchCombineZextTrunc(MachineInstr &MI, Register &Reg) { in matchCombineZextTrunc()
2450 Register DstReg = MI.getOperand(0).getReg(); in matchCombineZextTrunc()
2451 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineZextTrunc()
2463 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in matchCombineExtOfExt() argument
2468 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineExtOfExt()
2484 MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) { in applyCombineExtOfExt() argument
2490 Register Reg = std::get<0>(MatchInfo); in applyCombineExtOfExt()
2507 Register DstReg = MI.getOperand(0).getReg(); in applyCombineExtOfExt()
2516 Register DstReg = MI.getOperand(0).getReg(); in applyCombineMulByNegativeOne()
2517 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineMulByNegativeOne()
2526 bool CombinerHelper::matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg) { in matchCombineFNegOfFNeg()
2528 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineFNegOfFNeg()
2532 bool CombinerHelper::matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src) { in matchCombineFAbsOfFAbs()
2535 Register AbsSrc; in matchCombineFAbsOfFAbs()
2540 MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) { in matchCombineTruncOfExt() argument
2542 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineTruncOfExt()
2554 MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) { in applyCombineTruncOfExt() argument
2556 Register SrcReg = MatchInfo.first; in applyCombineTruncOfExt()
2558 Register DstReg = MI.getOperand(0).getReg(); in applyCombineTruncOfExt()
2575 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in matchCombineTruncOfShl() argument
2577 Register DstReg = MI.getOperand(0).getReg(); in matchCombineTruncOfShl()
2578 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineTruncOfShl()
2580 Register ShiftSrc; in matchCombineTruncOfShl()
2581 Register ShiftAmt; in matchCombineTruncOfShl()
2599 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in applyCombineTruncOfShl() argument
2601 Register DstReg = MI.getOperand(0).getReg(); in applyCombineTruncOfShl()
2602 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineTruncOfShl()
2606 Register ShiftSrc = MatchInfo.first; in applyCombineTruncOfShl()
2607 Register ShiftAmt = MatchInfo.second; in applyCombineTruncOfShl()
2744 Register OldReg = MI.getOperand(0).getReg(); in replaceSingleDefInstWithOperand()
2745 Register Replacement = MI.getOperand(OpIdx).getReg(); in replaceSingleDefInstWithOperand()
2753 Register Replacement) { in replaceSingleDefInstWithReg()
2755 Register OldReg = MI.getOperand(0).getReg(); in replaceSingleDefInstWithReg()
2827 MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) { in matchSimplifyAddToSub() argument
2828 Register LHS = MI.getOperand(1).getReg(); in matchSimplifyAddToSub()
2829 Register RHS = MI.getOperand(2).getReg(); in matchSimplifyAddToSub()
2830 Register &NewLHS = std::get<0>(MatchInfo); in matchSimplifyAddToSub()
2831 Register &NewRHS = std::get<1>(MatchInfo); in matchSimplifyAddToSub()
2836 auto CheckFold = [&](Register &MaybeSub, Register &MaybeNewLHS) { in matchSimplifyAddToSub()
2847 MachineInstr &MI, SmallVectorImpl<Register> &MatchInfo) { in matchCombineInsertVecElts()
2850 Register DstReg = MI.getOperand(0).getReg(); in matchCombineInsertVecElts()
2862 Register TmpReg; in matchCombineInsertVecElts()
2888 MachineInstr &MI, SmallVectorImpl<Register> &MatchInfo) { in applyCombineInsertVecElts()
2890 Register UndefReg; in applyCombineInsertVecElts()
2907 MachineInstr &MI, std::tuple<Register, Register> &MatchInfo) { in applySimplifyAddToSub() argument
2909 Register SubLHS, SubRHS; in applySimplifyAddToSub()
2928 Register Dst = MI.getOperand(0).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2929 Register LHSReg = MI.getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2930 Register RHSReg = MI.getOperand(2).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2950 Register X = LeftHandInst->getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2951 Register Y = RightHandInst->getOperand(1).getReg(); in matchHoistLogicOpWithSameOpcodeHands()
2960 Register ExtraHandOpSrcReg; in matchHoistLogicOpWithSameOpcodeHands()
3022 MachineInstr &MI, std::tuple<Register, int64_t> &MatchInfo) { in matchAshrShlToSextInreg() argument
3025 Register Src; in matchAshrShlToSextInreg()
3040 MachineInstr &MI, std::tuple<Register, int64_t> &MatchInfo) { in applyAshShlToSextInreg() argument
3042 Register Src; in applyAshShlToSextInreg()
3056 Register Dst = MI.getOperand(0).getReg(); in matchOverlappingAnd()
3059 Register R; in matchOverlappingAnd()
3079 Register &Replacement) { in matchRedundantAnd()
3099 Register AndDst = MI.getOperand(0).getReg(); in matchRedundantAnd()
3106 Register LHS = MI.getOperand(1).getReg(); in matchRedundantAnd()
3107 Register RHS = MI.getOperand(2).getReg(); in matchRedundantAnd()
3133 bool CombinerHelper::matchRedundantOr(MachineInstr &MI, Register &Replacement) { in matchRedundantOr()
3145 Register OrDst = MI.getOperand(0).getReg(); in matchRedundantOr()
3152 Register LHS = MI.getOperand(1).getReg(); in matchRedundantOr()
3153 Register RHS = MI.getOperand(2).getReg(); in matchRedundantOr()
3181 Register Src = MI.getOperand(1).getReg(); in matchRedundantSExtInReg()
3195 SmallVectorImpl<Register> &RegsToNegate) { in matchNotCmp()
3199 Register XorSrc; in matchNotCmp()
3200 Register CstReg; in matchNotCmp()
3217 Register Reg = RegsToNegate[I]; in matchNotCmp()
3272 SmallVectorImpl<Register> &RegsToNegate) { in applyNotCmp()
3273 for (Register Reg : RegsToNegate) { in applyNotCmp()
3304 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in matchXorOfAndWithSameReg() argument
3307 Register &X = MatchInfo.first; in matchXorOfAndWithSameReg()
3308 Register &Y = MatchInfo.second; in matchXorOfAndWithSameReg()
3309 Register AndReg = MI.getOperand(1).getReg(); in matchXorOfAndWithSameReg()
3310 Register SharedReg = MI.getOperand(2).getReg(); in matchXorOfAndWithSameReg()
3335 MachineInstr &MI, std::pair<Register, Register> &MatchInfo) { in applyXorOfAndWithSameReg() argument
3338 Register X, Y; in applyXorOfAndWithSameReg()
3349 Register DstReg = MI.getOperand(0).getReg(); in matchPtrAddZero()
3375 Register DstReg = MI.getOperand(0).getReg(); in applySimplifyURemByPow2()
3376 Register Src0 = MI.getOperand(1).getReg(); in applySimplifyURemByPow2()
3377 Register Pow2Src1 = MI.getOperand(2).getReg(); in applySimplifyURemByPow2()
3388 Optional<SmallVector<Register, 8>>
3414 SmallVector<Register, 8> RegsToVisit; in findCandidatesForLoadOrCombine()
3425 Register OrLHS = Curr->getOperand(1).getReg(); in findCandidatesForLoadOrCombine()
3426 Register OrRHS = Curr->getOperand(2).getReg(); in findCandidatesForLoadOrCombine()
3460 matchLoadAndBytePosition(Register Reg, unsigned MemSizeInBits, in matchLoadAndBytePosition()
3464 Register MaybeLoad; in matchLoadAndBytePosition()
3489 const SmallVector<Register, 8> &RegsToVisit, const unsigned MemSizeInBits) { in findLoadOffsetsForLoadOrCombine() argument
3515 Register BasePtr; in findLoadOffsetsForLoadOrCombine()
3547 Register LoadPtr; in findLoadOffsetsForLoadOrCombine()
3634 Register Dst = MI.getOperand(0).getReg(); in matchLoadOrCombine()
3705 Register Ptr = LowestIdxLoad->getPointerReg(); in matchLoadOrCombine()
3727 Register LoadDst = NeedsBSwap ? MRI.cloneVirtualRegister(Dst) : Dst; in matchLoadOrCombine()
3739 Register DstReg = MI.getOperand(0).getReg(); in matchExtendThroughPhis()
3793 Register DstReg = ExtMI->getOperand(0).getReg(); in applyExtendThroughPhis()
3837 Register &Reg) { in matchExtractVecEltBuildVec()
3841 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec()
3874 Register &Reg) { in applyExtractVecEltBuildVec()
3878 Register DstReg = MI.getOperand(0).getReg(); in applyExtractVecEltBuildVec()
3893 SmallVectorImpl<std::pair<Register, MachineInstr *>> &SrcDstPairs) { in matchExtractAllEltsFromBuildVector() argument
3911 Register DstReg = MI.getOperand(0).getReg(); in matchExtractAllEltsFromBuildVector()
3936 SmallVectorImpl<std::pair<Register, MachineInstr *>> &SrcDstPairs) { in applyExtractAllEltsFromBuildVector() argument
3963 Register X = MI.getOperand(1).getReg(); in matchFunnelShiftToRotate()
3964 Register Y = MI.getOperand(2).getReg(); in matchFunnelShiftToRotate()
3989 Register AmtReg = MI.getOperand(2).getReg(); in matchRotateOutOfRange()
4005 Register Amt = MI.getOperand(2).getReg(); in applyRotateOutOfRange()
4071 Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromSExtInReg()
4072 Register Src = MI.getOperand(1).getReg(); in matchBitfieldExtractFromSExtInReg()
4078 Register ShiftSrc; in matchBitfieldExtractFromSExtInReg()
4100 Register Dst = MI.getOperand(0).getReg(); in matchBitfieldExtractFromAnd()
4107 Register ShiftSrc; in matchBitfieldExtractFromAnd()
4137 Register Src1Reg = PtrAdd.getOperand(1).getReg(); in reassociationCanBreakAddressingModePattern()
4142 Register Src2Reg = PtrAdd.getOperand(2).getReg(); in reassociationCanBreakAddressingModePattern()
4165 Register DefReg = ConvUseMI->getOperand(0).getReg(); in reassociationCanBreakAddressingModePattern()
4212 Register Src1Reg = MI.getOperand(1).getReg(); in matchReassocPtrAdd()
4213 Register Src2Reg = MI.getOperand(2).getReg(); in matchReassocPtrAdd()
4237 Register LHSSrc1 = LHS->getOperand(1).getReg(); in matchReassocPtrAdd()
4238 Register LHSSrc2 = LHS->getOperand(2).getReg(); in matchReassocPtrAdd()
4258 Register Op1 = MI.getOperand(1).getReg(); in matchConstantFold()
4259 Register Op2 = MI.getOperand(2).getReg(); in matchConstantFold()