Lines Matching refs:Register
100 Register VirtReg; ///< Virtual register number.
106 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
109 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
119 DenseMap<Register, MCPhysReg> BundleVirtRegsMap;
245 Register Reg) const;
258 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
259 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
262 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
263 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
267 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
270 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
273 Register VirtReg);
274 void defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
276 void useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
280 SmallSet<Register, 2> &PrologLiveIns) const;
285 Register traceCopies(Register VirtReg) const;
286 Register traceCopyChain(Register Reg) const;
288 int getStackSpaceFor(Register VirtReg);
289 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
291 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
294 bool mayLiveOut(Register VirtReg);
295 bool mayLiveIn(Register VirtReg);
322 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
355 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut()
356 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) { in mayLiveOut()
368 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
379 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
389 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
399 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn()
400 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) in mayLiveIn()
408 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveIn()
418 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill()
474 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload()
490 MachineBasicBlock &MBB, SmallSet<Register, 2> &PrologLiveIns) const { in getMBBBeginInsertionPoint() argument
528 SmallSet<Register, 2> PrologLiveIns; in reloadAtBegin()
561 assert(Register::isPhysicalRegister(Reg) && "expected physreg"); in usePhysReg()
654 Register VirtReg, MCPhysReg Reg) { in assignDanglingDebugValues()
691 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
706 Register RegAllocFast::traceCopyChain(Register Reg) const { in traceCopyChain()
725 Register RegAllocFast::traceCopies(Register VirtReg) const { in traceCopies()
730 Register Reg = MI.getOperand(1).getReg(); in traceCopies()
739 return Register(); in traceCopies()
744 Register Hint0, bool LookAtPhysRegUses) { in allocVirtReg()
745 const Register VirtReg = LR.VirtReg; in allocVirtReg()
767 Hint0 = Register(); in allocVirtReg()
772 Register Hint1 = traceCopies(VirtReg); in allocVirtReg()
786 Hint1 = Register(); in allocVirtReg()
835 Register VirtReg = MO.getReg(); in allocVirtRegUndef()
836 assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg"); in allocVirtRegUndef()
861 Register VirtReg) { in defineLiveThroughVirtReg()
893 Register VirtReg, bool LookAtPhysRegUses) { in defineVirtReg()
943 Register VirtReg) { in useVirtReg()
966 Register Hint; in useVirtReg()
1058 Register VirtReg = LR.VirtReg; in dumpState()
1062 assert(Register::isPhysicalRegister(PhysReg) && in dumpState()
1074 Register Reg) const { in addRegClassDefCounts()
1128 Register Reg = MO.getReg(); in allocateInstruction()
1182 Register Reg = MO.getReg(); in allocateInstruction()
1202 Register Reg0 = MO0.getReg(); in allocateInstruction()
1203 Register Reg1 = MO1.getReg(); in allocateInstruction()
1250 Register Reg = MO.getReg(); in allocateInstruction()
1278 Register Reg = MO.getReg(); in allocateInstruction()
1309 Register Reg = MO.getReg(); in allocateInstruction()
1326 Register Reg = MO.getReg(); in allocateInstruction()
1353 Register Reg = MO.getReg(); in allocateInstruction()
1375 Register Reg = MO.getReg(); in allocateInstruction()
1404 for (Register Reg : MI.getUsedDebugRegs()) { in handleDebugValue()
1405 if (!Register::isVirtualRegister(Reg)) in handleDebugValue()
1447 Register Reg = MO.getReg(); in handleBundle()
1451 DenseMap<Register, MCPhysReg>::iterator DI; in handleBundle()