114   DenseMap<Register, Register> SrcRegMap;
119   DenseMap<Register, Register> DstRegMap;
121   bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
123   bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
125   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131   bool isProfitableToConv3Addr(Register RegA, Register RegB);
134                           MachineBasicBlock::iterator &nmi, Register RegA,
135                           Register RegB, unsigned Dist);
137   bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
140                              MachineBasicBlock::iterator &nmi, Register Reg);
142                              MachineBasicBlock::iterator &nmi, Register Reg);
154   void scanUses(Register DstReg);
200 static bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS);
203 static MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB,  in getSingleDef()
224 bool TwoAddressInstructionPass::isRevCopyChain(Register FromReg, Register ToReg,  in isRevCopyChain()
226   Register TmpReg = FromReg;  in isRevCopyChain()
244 bool TwoAddressInstructionPass::noUseAfterLastDef(Register Reg, unsigned Dist,  in noUseAfterLastDef()
268                         Register &SrcReg, Register &DstReg, bool &IsSrcPhys,  in isCopyToReg()
289 static bool isPlainlyKilled(MachineInstr *MI, Register Reg,  in isPlainlyKilled()
330 static bool isKilled(MachineInstr &MI, Register Reg,  in isKilled()
349     Register SrcReg, DstReg;  in isKilled()
360 static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) {  in isTwoAddrUse()
377 findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,  in findOnlyInterestingUse()
379                        bool &IsCopy, Register &DstReg, bool &IsDstPhys) {  in findOnlyInterestingUse()
386   Register SrcReg;  in findOnlyInterestingUse()
402 static MCRegister getMappedReg(Register Reg,  in getMappedReg()
403                                DenseMap<Register, Register> &RegMap) {  in getMappedReg()  argument
405     DenseMap<Register, Register>::iterator SI = RegMap.find(Reg);  in getMappedReg()
416 static bool regsAreCompatible(Register RegA, Register RegB,  in regsAreCompatible()
426 static bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg,  in regOverlapsSet()
437 bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,  in isProfitableToCommute()
438                                                       Register RegB,  in isProfitableToCommute()
439                                                       Register RegC,  in isProfitableToCommute()
547   Register RegC = MI->getOperand(RegCIdx).getReg();  in commuteInstruction()
564     Register RegA = MI->getOperand(DstIdx).getReg();  in commuteInstruction()
573 bool TwoAddressInstructionPass::isProfitableToConv3Addr(Register RegA,  in isProfitableToConv3Addr()
574                                                         Register RegB) {  in isProfitableToConv3Addr()
592     Register RegA, Register RegB, unsigned Dist) {  in convertInstTo3Addr()
639 void TwoAddressInstructionPass::scanUses(Register DstReg) {  in scanUses()
640   SmallVector<Register, 4> VirtRegPairs;  in scanUses()
643   Register NewReg;  in scanUses()
644   Register Reg = DstReg;  in scanUses()
700   Register SrcReg, DstReg;  in processCopy()
723     Register Reg) {  in rescheduleMIBelowKill()
760   Register DstReg;  in rescheduleMIBelowKill()
772   SmallVector<Register, 2> Uses;  in rescheduleMIBelowKill()
773   SmallVector<Register, 2> Kills;  in rescheduleMIBelowKill()
774   SmallVector<Register, 2> Defs;  in rescheduleMIBelowKill()
778     Register MOReg = MO.getReg();  in rescheduleMIBelowKill()
822       Register MOReg = MO.getReg();  in rescheduleMIBelowKill()
889 bool TwoAddressInstructionPass::isDefTooClose(Register Reg, unsigned Dist,  in isDefTooClose()
912     Register Reg) {  in rescheduleKillAboveMI()
944   Register DstReg;  in rescheduleKillAboveMI()
952   SmallVector<Register, 2> Uses;  in rescheduleKillAboveMI()
953   SmallVector<Register, 2> Kills;  in rescheduleKillAboveMI()
954   SmallVector<Register, 2> Defs;  in rescheduleKillAboveMI()
955   SmallVector<Register, 2> LiveDefs;  in rescheduleKillAboveMI()
959     Register MOReg = MO.getReg();  in rescheduleKillAboveMI()
992     SmallVector<Register, 2> OtherDefs;  in rescheduleKillAboveMI()
996       Register MOReg = MO.getReg();  in rescheduleKillAboveMI()
1017       Register MOReg = OtherDefs[i];  in rescheduleKillAboveMI()
1073   Register DstOpReg = MI->getOperand(DstOpIdx).getReg();  in tryInstructionCommute()
1074   Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();  in tryInstructionCommute()
1086     Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();  in tryInstructionCommute()
1138   Register regA = MI.getOperand(DstIdx).getReg();  in tryInstructionTransform()
1139   Register regB = MI.getOperand(SrcIdx).getReg();  in tryInstructionTransform()
1224         Register Reg = MRI->createVirtualRegister(RC);  in tryInstructionTransform()
1285           SmallVector<Register, 4> OrigRegs;  in tryInstructionTransform()
1334     Register SrcReg = SrcMO.getReg();  in collectTiedOperands()
1335     Register DstReg = DstMO.getReg();  in collectTiedOperands()
1373   Register RegB = 0;  in processTiedPairs()
1380     Register RegA = DstMO.getReg();  in processTiedPairs()
1600           Register SrcReg = mi->getOperand(SrcIdx).getReg();  in runOnMachineFunction()
1601           Register DstReg = mi->getOperand(DstIdx).getReg();  in runOnMachineFunction()
1659   Register DstReg = MI.getOperand(0).getReg();  in eliminateRegSequence()
1666   SmallVector<Register, 4> OrigRegs;  in eliminateRegSequence()
1676     Register SrcReg = UseMO.getReg();  in eliminateRegSequence()