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Searched refs:getRegClassName (Results 1 – 25 of 27) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DLiveStacks.cpp84 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
H A DRegAllocBase.cpp107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
H A DRegisterClassInfo.cpp155 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
H A DVirtRegMap.cpp146 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
154 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
H A DMachineVerifier.cpp1303 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
1373 << TRI->getRegClassName( in visitMachineOperand()
1386 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1392 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1415 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
1416 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
H A DTargetRegisterInfo.cpp159 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
H A DLiveRangeEdit.cpp471 << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; in calculateRegClassAndHint()
H A DExecutionDomainFix.cpp424 << TRI->getRegClassName(RC) << " **********\n"); in runOnMachineFunction()
H A DRegisterScavenging.cpp513 TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) + in spill()
H A DRegAllocPBQP.cpp883 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); in PrintNodeInfo()
H A DAggressiveAntiDepBreaker.cpp545 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); in GetRenameRegisters()
H A DRegAllocFast.cpp570 << " in class " << TRI->getRegClassName(&RC) << '\n'); in allocVirtReg()
H A DInlineSpiller.cpp1086 << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) in spill()
H A DRegisterCoalescer.cpp1818 << TRI->getRegClassName(CP.getNewRC()) << " with "; in joinCopy()
3670 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); in runOnMachineFunction()
H A DMachineInstr.cpp1615 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp111 OS << TRI->getRegClassName(&RC); in print()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp374 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
376 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
399 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
437 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
H A DAMDGPUDisassembler.h60 const char* getRegClassName(unsigned RegClassID) const;
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h702 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
703 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp95 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
H A DHexagonBitTracker.cpp109 << TRI.getRegClassName(&RC) << '\n'; in mask()
H A DHexagonFrameLowering.cpp2176 dbgs() << HRI.getRegClassName(P.second.RC) << '\n'; in optimizeSpillSlots()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h438 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
/freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp854 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC)); in initNames2RegClasses()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp2060 LLVM_DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / " in dumpRegPressure()

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