1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonBitTracker.h"
11 #include "Hexagon.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonSubtarget.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetRegisterInfo.h"
21 #include "llvm/IR/Argument.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Type.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <cstdlib>
34 #include <utility>
35 #include <vector>
36 
37 using namespace llvm;
38 
39 using BT = BitTracker;
40 
HexagonEvaluator(const HexagonRegisterInfo & tri,MachineRegisterInfo & mri,const HexagonInstrInfo & tii,MachineFunction & mf)41 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
42                                    MachineRegisterInfo &mri,
43                                    const HexagonInstrInfo &tii,
44                                    MachineFunction &mf)
45     : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
46   // Populate the VRX map (VR to extension-type).
47   // Go over all the formal parameters of the function. If a given parameter
48   // P is sign- or zero-extended, locate the virtual register holding that
49   // parameter and create an entry in the VRX map indicating the type of ex-
50   // tension (and the source type).
51   // This is a bit complicated to do accurately, since the memory layout in-
52   // formation is necessary to precisely determine whether an aggregate para-
53   // meter will be passed in a register or in memory. What is given in MRI
54   // is the association between the physical register that is live-in (i.e.
55   // holds an argument), and the virtual register that this value will be
56   // copied into. This, by itself, is not sufficient to map back the virtual
57   // register to a formal parameter from Function (since consecutive live-ins
58   // from MRI may not correspond to consecutive formal parameters from Func-
59   // tion). To avoid the complications with in-memory arguments, only consi-
60   // der the initial sequence of formal parameters that are known to be
61   // passed via registers.
62   unsigned InVirtReg, InPhysReg = 0;
63 
64   for (const Argument &Arg : MF.getFunction().args()) {
65     Type *ATy = Arg.getType();
66     unsigned Width = 0;
67     if (ATy->isIntegerTy())
68       Width = ATy->getIntegerBitWidth();
69     else if (ATy->isPointerTy())
70       Width = 32;
71     // If pointer size is not set through target data, it will default to
72     // Module::AnyPointerSize.
73     if (Width == 0 || Width > 64)
74       break;
75     if (Arg.hasAttribute(Attribute::ByVal))
76       continue;
77     InPhysReg = getNextPhysReg(InPhysReg, Width);
78     if (!InPhysReg)
79       break;
80     InVirtReg = getVirtRegFor(InPhysReg);
81     if (!InVirtReg)
82       continue;
83     if (Arg.hasAttribute(Attribute::SExt))
84       VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
85     else if (Arg.hasAttribute(Attribute::ZExt))
86       VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
87   }
88 }
89 
mask(unsigned Reg,unsigned Sub) const90 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
91   if (Sub == 0)
92     return MachineEvaluator::mask(Reg, 0);
93   const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
94   unsigned ID = RC.getID();
95   uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
96   const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
97   bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
98   switch (ID) {
99     case Hexagon::DoubleRegsRegClassID:
100     case Hexagon::HvxWRRegClassID:
101     case Hexagon::HvxVQRRegClassID:
102       return IsSubLo ? BT::BitMask(0, RW-1)
103                      : BT::BitMask(RW, 2*RW-1);
104     default:
105       break;
106   }
107 #ifndef NDEBUG
108   dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
109          << TRI.getRegClassName(&RC) << '\n';
110 #endif
111   llvm_unreachable("Unexpected register/subregister");
112 }
113 
getPhysRegBitWidth(unsigned Reg) const114 uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
115   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
116 
117   using namespace Hexagon;
118   const auto &HST = MF.getSubtarget<HexagonSubtarget>();
119   if (HST.useHVXOps()) {
120     for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
121                      HvxVQRRegClass})
122       if (RC.contains(Reg))
123         return TRI.getRegSizeInBits(RC);
124   }
125   // Default treatment for other physical registers.
126   if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
127     return TRI.getRegSizeInBits(*RC);
128 
129   llvm_unreachable(
130       (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
131 }
132 
composeWithSubRegIndex(const TargetRegisterClass & RC,unsigned Idx) const133 const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
134       const TargetRegisterClass &RC, unsigned Idx) const {
135   if (Idx == 0)
136     return RC;
137 
138 #ifndef NDEBUG
139   const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
140   bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
141   bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
142   assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
143 #endif
144 
145   switch (RC.getID()) {
146     case Hexagon::DoubleRegsRegClassID:
147       return Hexagon::IntRegsRegClass;
148     case Hexagon::HvxWRRegClassID:
149       return Hexagon::HvxVRRegClass;
150     case Hexagon::HvxVQRRegClassID:
151       return Hexagon::HvxWRRegClass;
152     default:
153       break;
154   }
155 #ifndef NDEBUG
156   dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
157 #endif
158   llvm_unreachable("Unimplemented combination of reg class/subreg idx");
159 }
160 
161 namespace {
162 
163 class RegisterRefs {
164   std::vector<BT::RegisterRef> Vector;
165 
166 public:
RegisterRefs(const MachineInstr & MI)167   RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
168     for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
169       const MachineOperand &MO = MI.getOperand(i);
170       if (MO.isReg())
171         Vector[i] = BT::RegisterRef(MO);
172       // For indices that don't correspond to registers, the entry will
173       // remain constructed via the default constructor.
174     }
175   }
176 
size() const177   size_t size() const { return Vector.size(); }
178 
operator [](unsigned n) const179   const BT::RegisterRef &operator[](unsigned n) const {
180     // The main purpose of this operator is to assert with bad argument.
181     assert(n < Vector.size());
182     return Vector[n];
183   }
184 };
185 
186 } // end anonymous namespace
187 
evaluate(const MachineInstr & MI,const CellMapType & Inputs,CellMapType & Outputs) const188 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
189                                 const CellMapType &Inputs,
190                                 CellMapType &Outputs) const {
191   using namespace Hexagon;
192 
193   unsigned NumDefs = 0;
194 
195   // Sanity verification: there should not be any defs with subregisters.
196   for (const MachineOperand &MO : MI.operands()) {
197     if (!MO.isReg() || !MO.isDef())
198       continue;
199     NumDefs++;
200     assert(MO.getSubReg() == 0);
201   }
202 
203   if (NumDefs == 0)
204     return false;
205 
206   unsigned Opc = MI.getOpcode();
207 
208   if (MI.mayLoad()) {
209     switch (Opc) {
210       // These instructions may be marked as mayLoad, but they are generating
211       // immediate values, so skip them.
212       case CONST32:
213       case CONST64:
214         break;
215       default:
216         return evaluateLoad(MI, Inputs, Outputs);
217     }
218   }
219 
220   // Check COPY instructions that copy formal parameters into virtual
221   // registers. Such parameters can be sign- or zero-extended at the
222   // call site, and we should take advantage of this knowledge. The MRI
223   // keeps a list of pairs of live-in physical and virtual registers,
224   // which provides information about which virtual registers will hold
225   // the argument values. The function will still contain instructions
226   // defining those virtual registers, and in practice those are COPY
227   // instructions from a physical to a virtual register. In such cases,
228   // applying the argument extension to the virtual register can be seen
229   // as simply mirroring the extension that had already been applied to
230   // the physical register at the call site. If the defining instruction
231   // was not a COPY, it would not be clear how to mirror that extension
232   // on the callee's side. For that reason, only check COPY instructions
233   // for potential extensions.
234   if (MI.isCopy()) {
235     if (evaluateFormalCopy(MI, Inputs, Outputs))
236       return true;
237   }
238 
239   // Beyond this point, if any operand is a global, skip that instruction.
240   // The reason is that certain instructions that can take an immediate
241   // operand can also have a global symbol in that operand. To avoid
242   // checking what kind of operand a given instruction has individually
243   // for each instruction, do it here. Global symbols as operands gene-
244   // rally do not provide any useful information.
245   for (const MachineOperand &MO : MI.operands()) {
246     if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
247         MO.isCPI())
248       return false;
249   }
250 
251   RegisterRefs Reg(MI);
252 #define op(i) MI.getOperand(i)
253 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
254 #define im(i) MI.getOperand(i).getImm()
255 
256   // If the instruction has no register operands, skip it.
257   if (Reg.size() == 0)
258     return false;
259 
260   // Record result for register in operand 0.
261   auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
262         -> bool {
263     putCell(Reg[0], Val, Outputs);
264     return true;
265   };
266   // Get the cell corresponding to the N-th operand.
267   auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
268                                         uint16_t W) -> BT::RegisterCell {
269     const MachineOperand &Op = MI.getOperand(N);
270     if (Op.isImm())
271       return eIMM(Op.getImm(), W);
272     if (!Op.isReg())
273       return RegisterCell::self(0, W);
274     assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
275     return rc(N);
276   };
277   // Extract RW low bits of the cell.
278   auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
279         -> BT::RegisterCell {
280     assert(RW <= RC.width());
281     return eXTR(RC, 0, RW);
282   };
283   // Extract RW high bits of the cell.
284   auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
285         -> BT::RegisterCell {
286     uint16_t W = RC.width();
287     assert(RW <= W);
288     return eXTR(RC, W-RW, W);
289   };
290   // Extract N-th halfword (counting from the least significant position).
291   auto half = [this] (const BT::RegisterCell &RC, unsigned N)
292         -> BT::RegisterCell {
293     assert(N*16+16 <= RC.width());
294     return eXTR(RC, N*16, N*16+16);
295   };
296   // Shuffle bits (pick even/odd from cells and merge into result).
297   auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
298                          uint16_t BW, bool Odd) -> BT::RegisterCell {
299     uint16_t I = Odd, Ws = Rs.width();
300     assert(Ws == Rt.width());
301     RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
302     I += 2;
303     while (I*BW < Ws) {
304       RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
305       I += 2;
306     }
307     return RC;
308   };
309 
310   // The bitwidth of the 0th operand. In most (if not all) of the
311   // instructions below, the 0th operand is the defined register.
312   // Pre-compute the bitwidth here, because it is needed in many cases
313   // cases below.
314   uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
315 
316   // Register id of the 0th operand. It can be 0.
317   unsigned Reg0 = Reg[0].Reg;
318 
319   switch (Opc) {
320     // Transfer immediate:
321 
322     case A2_tfrsi:
323     case A2_tfrpi:
324     case CONST32:
325     case CONST64:
326       return rr0(eIMM(im(1), W0), Outputs);
327     case PS_false:
328       return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
329     case PS_true:
330       return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
331     case PS_fi: {
332       int FI = op(1).getIndex();
333       int Off = op(2).getImm();
334       unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
335       unsigned L = countTrailingZeros(A);
336       RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
337       RC.fill(0, L, BT::BitValue::Zero);
338       return rr0(RC, Outputs);
339     }
340 
341     // Transfer register:
342 
343     case A2_tfr:
344     case A2_tfrp:
345     case C2_pxfer_map:
346       return rr0(rc(1), Outputs);
347     case C2_tfrpr: {
348       uint16_t RW = W0;
349       uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
350       assert(PW <= RW);
351       RegisterCell PC = eXTR(rc(1), 0, PW);
352       RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
353       RC.fill(PW, RW, BT::BitValue::Zero);
354       return rr0(RC, Outputs);
355     }
356     case C2_tfrrp: {
357       uint16_t RW = W0;
358       uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
359       RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW);
360       RC.fill(PW, RW, BT::BitValue::Zero);
361       return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
362     }
363 
364     // Arithmetic:
365 
366     case A2_abs:
367     case A2_absp:
368       // TODO
369       break;
370 
371     case A2_addsp: {
372       uint16_t W1 = getRegBitWidth(Reg[1]);
373       assert(W0 == 64 && W1 == 32);
374       RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
375       RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
376       return rr0(RC, Outputs);
377     }
378     case A2_add:
379     case A2_addp:
380       return rr0(eADD(rc(1), rc(2)), Outputs);
381     case A2_addi:
382       return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
383     case S4_addi_asl_ri: {
384       RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
385       return rr0(RC, Outputs);
386     }
387     case S4_addi_lsr_ri: {
388       RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
389       return rr0(RC, Outputs);
390     }
391     case S4_addaddi: {
392       RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
393       return rr0(RC, Outputs);
394     }
395     case M4_mpyri_addi: {
396       RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
397       RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
398       return rr0(RC, Outputs);
399     }
400     case M4_mpyrr_addi: {
401       RegisterCell M = eMLS(rc(2), rc(3));
402       RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
403       return rr0(RC, Outputs);
404     }
405     case M4_mpyri_addr_u2: {
406       RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
407       RegisterCell RC = eADD(rc(1), lo(M, W0));
408       return rr0(RC, Outputs);
409     }
410     case M4_mpyri_addr: {
411       RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
412       RegisterCell RC = eADD(rc(1), lo(M, W0));
413       return rr0(RC, Outputs);
414     }
415     case M4_mpyrr_addr: {
416       RegisterCell M = eMLS(rc(2), rc(3));
417       RegisterCell RC = eADD(rc(1), lo(M, W0));
418       return rr0(RC, Outputs);
419     }
420     case S4_subaddi: {
421       RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
422       return rr0(RC, Outputs);
423     }
424     case M2_accii: {
425       RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
426       return rr0(RC, Outputs);
427     }
428     case M2_acci: {
429       RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
430       return rr0(RC, Outputs);
431     }
432     case M2_subacc: {
433       RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
434       return rr0(RC, Outputs);
435     }
436     case S2_addasl_rrri: {
437       RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
438       return rr0(RC, Outputs);
439     }
440     case C4_addipc: {
441       RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
442       RPC.fill(0, 2, BT::BitValue::Zero);
443       return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
444     }
445     case A2_sub:
446     case A2_subp:
447       return rr0(eSUB(rc(1), rc(2)), Outputs);
448     case A2_subri:
449       return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
450     case S4_subi_asl_ri: {
451       RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
452       return rr0(RC, Outputs);
453     }
454     case S4_subi_lsr_ri: {
455       RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
456       return rr0(RC, Outputs);
457     }
458     case M2_naccii: {
459       RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
460       return rr0(RC, Outputs);
461     }
462     case M2_nacci: {
463       RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
464       return rr0(RC, Outputs);
465     }
466     // 32-bit negation is done by "Rd = A2_subri 0, Rs"
467     case A2_negp:
468       return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
469 
470     case M2_mpy_up: {
471       RegisterCell M = eMLS(rc(1), rc(2));
472       return rr0(hi(M, W0), Outputs);
473     }
474     case M2_dpmpyss_s0:
475       return rr0(eMLS(rc(1), rc(2)), Outputs);
476     case M2_dpmpyss_acc_s0:
477       return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
478     case M2_dpmpyss_nac_s0:
479       return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
480     case M2_mpyi: {
481       RegisterCell M = eMLS(rc(1), rc(2));
482       return rr0(lo(M, W0), Outputs);
483     }
484     case M2_macsip: {
485       RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
486       RegisterCell RC = eADD(rc(1), lo(M, W0));
487       return rr0(RC, Outputs);
488     }
489     case M2_macsin: {
490       RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
491       RegisterCell RC = eSUB(rc(1), lo(M, W0));
492       return rr0(RC, Outputs);
493     }
494     case M2_maci: {
495       RegisterCell M = eMLS(rc(2), rc(3));
496       RegisterCell RC = eADD(rc(1), lo(M, W0));
497       return rr0(RC, Outputs);
498     }
499     case M2_mpysmi: {
500       RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
501       return rr0(lo(M, 32), Outputs);
502     }
503     case M2_mpysin: {
504       RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
505       return rr0(lo(M, 32), Outputs);
506     }
507     case M2_mpysip: {
508       RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
509       return rr0(lo(M, 32), Outputs);
510     }
511     case M2_mpyu_up: {
512       RegisterCell M = eMLU(rc(1), rc(2));
513       return rr0(hi(M, W0), Outputs);
514     }
515     case M2_dpmpyuu_s0:
516       return rr0(eMLU(rc(1), rc(2)), Outputs);
517     case M2_dpmpyuu_acc_s0:
518       return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
519     case M2_dpmpyuu_nac_s0:
520       return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
521     //case M2_mpysu_up:
522 
523     // Logical/bitwise:
524 
525     case A2_andir:
526       return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
527     case A2_and:
528     case A2_andp:
529       return rr0(eAND(rc(1), rc(2)), Outputs);
530     case A4_andn:
531     case A4_andnp:
532       return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
533     case S4_andi_asl_ri: {
534       RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
535       return rr0(RC, Outputs);
536     }
537     case S4_andi_lsr_ri: {
538       RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
539       return rr0(RC, Outputs);
540     }
541     case M4_and_and:
542       return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
543     case M4_and_andn:
544       return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
545     case M4_and_or:
546       return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
547     case M4_and_xor:
548       return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
549     case A2_orir:
550       return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
551     case A2_or:
552     case A2_orp:
553       return rr0(eORL(rc(1), rc(2)), Outputs);
554     case A4_orn:
555     case A4_ornp:
556       return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
557     case S4_ori_asl_ri: {
558       RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
559       return rr0(RC, Outputs);
560     }
561     case S4_ori_lsr_ri: {
562       RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
563       return rr0(RC, Outputs);
564     }
565     case M4_or_and:
566       return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
567     case M4_or_andn:
568       return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
569     case S4_or_andi:
570     case S4_or_andix: {
571       RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
572       return rr0(RC, Outputs);
573     }
574     case S4_or_ori: {
575       RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
576       return rr0(RC, Outputs);
577     }
578     case M4_or_or:
579       return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
580     case M4_or_xor:
581       return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
582     case A2_xor:
583     case A2_xorp:
584       return rr0(eXOR(rc(1), rc(2)), Outputs);
585     case M4_xor_and:
586       return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
587     case M4_xor_andn:
588       return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
589     case M4_xor_or:
590       return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
591     case M4_xor_xacc:
592       return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
593     case A2_not:
594     case A2_notp:
595       return rr0(eNOT(rc(1)), Outputs);
596 
597     case S2_asl_i_r:
598     case S2_asl_i_p:
599       return rr0(eASL(rc(1), im(2)), Outputs);
600     case A2_aslh:
601       return rr0(eASL(rc(1), 16), Outputs);
602     case S2_asl_i_r_acc:
603     case S2_asl_i_p_acc:
604       return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
605     case S2_asl_i_r_nac:
606     case S2_asl_i_p_nac:
607       return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
608     case S2_asl_i_r_and:
609     case S2_asl_i_p_and:
610       return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
611     case S2_asl_i_r_or:
612     case S2_asl_i_p_or:
613       return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
614     case S2_asl_i_r_xacc:
615     case S2_asl_i_p_xacc:
616       return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
617     case S2_asl_i_vh:
618     case S2_asl_i_vw:
619       // TODO
620       break;
621 
622     case S2_asr_i_r:
623     case S2_asr_i_p:
624       return rr0(eASR(rc(1), im(2)), Outputs);
625     case A2_asrh:
626       return rr0(eASR(rc(1), 16), Outputs);
627     case S2_asr_i_r_acc:
628     case S2_asr_i_p_acc:
629       return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
630     case S2_asr_i_r_nac:
631     case S2_asr_i_p_nac:
632       return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
633     case S2_asr_i_r_and:
634     case S2_asr_i_p_and:
635       return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
636     case S2_asr_i_r_or:
637     case S2_asr_i_p_or:
638       return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
639     case S2_asr_i_r_rnd: {
640       // The input is first sign-extended to 64 bits, then the output
641       // is truncated back to 32 bits.
642       assert(W0 == 32);
643       RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
644       RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
645       return rr0(eXTR(RC, 0, W0), Outputs);
646     }
647     case S2_asr_i_r_rnd_goodsyntax: {
648       int64_t S = im(2);
649       if (S == 0)
650         return rr0(rc(1), Outputs);
651       // Result: S2_asr_i_r_rnd Rs, u5-1
652       RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
653       RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
654       return rr0(eXTR(RC, 0, W0), Outputs);
655     }
656     case S2_asr_r_vh:
657     case S2_asr_i_vw:
658     case S2_asr_i_svw_trun:
659       // TODO
660       break;
661 
662     case S2_lsr_i_r:
663     case S2_lsr_i_p:
664       return rr0(eLSR(rc(1), im(2)), Outputs);
665     case S2_lsr_i_r_acc:
666     case S2_lsr_i_p_acc:
667       return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
668     case S2_lsr_i_r_nac:
669     case S2_lsr_i_p_nac:
670       return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
671     case S2_lsr_i_r_and:
672     case S2_lsr_i_p_and:
673       return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
674     case S2_lsr_i_r_or:
675     case S2_lsr_i_p_or:
676       return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
677     case S2_lsr_i_r_xacc:
678     case S2_lsr_i_p_xacc:
679       return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
680 
681     case S2_clrbit_i: {
682       RegisterCell RC = rc(1);
683       RC[im(2)] = BT::BitValue::Zero;
684       return rr0(RC, Outputs);
685     }
686     case S2_setbit_i: {
687       RegisterCell RC = rc(1);
688       RC[im(2)] = BT::BitValue::One;
689       return rr0(RC, Outputs);
690     }
691     case S2_togglebit_i: {
692       RegisterCell RC = rc(1);
693       uint16_t BX = im(2);
694       RC[BX] = RC[BX].is(0) ? BT::BitValue::One
695                             : RC[BX].is(1) ? BT::BitValue::Zero
696                                            : BT::BitValue::self();
697       return rr0(RC, Outputs);
698     }
699 
700     case A4_bitspliti: {
701       uint16_t W1 = getRegBitWidth(Reg[1]);
702       uint16_t BX = im(2);
703       // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
704       const BT::BitValue Zero = BT::BitValue::Zero;
705       RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
706                                         .fill(W1+(W1-BX), W0, Zero);
707       RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
708       RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
709       return rr0(RC, Outputs);
710     }
711     case S4_extract:
712     case S4_extractp:
713     case S2_extractu:
714     case S2_extractup: {
715       uint16_t Wd = im(2), Of = im(3);
716       assert(Wd <= W0);
717       if (Wd == 0)
718         return rr0(eIMM(0, W0), Outputs);
719       // If the width extends beyond the register size, pad the register
720       // with 0 bits.
721       RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
722       RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
723       // Ext is short, need to extend it with 0s or sign bit.
724       RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
725       if (Opc == S2_extractu || Opc == S2_extractup)
726         return rr0(eZXT(RC, Wd), Outputs);
727       return rr0(eSXT(RC, Wd), Outputs);
728     }
729     case S2_insert:
730     case S2_insertp: {
731       uint16_t Wd = im(3), Of = im(4);
732       assert(Wd < W0 && Of < W0);
733       // If Wd+Of exceeds W0, the inserted bits are truncated.
734       if (Wd+Of > W0)
735         Wd = W0-Of;
736       if (Wd == 0)
737         return rr0(rc(1), Outputs);
738       return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
739     }
740 
741     // Bit permutations:
742 
743     case A2_combineii:
744     case A4_combineii:
745     case A4_combineir:
746     case A4_combineri:
747     case A2_combinew:
748     case V6_vcombine:
749       assert(W0 % 2 == 0);
750       return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
751     case A2_combine_ll:
752     case A2_combine_lh:
753     case A2_combine_hl:
754     case A2_combine_hh: {
755       assert(W0 == 32);
756       assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
757       // Low half in the output is 0 for _ll and _hl, 1 otherwise:
758       unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
759       // High half in the output is 0 for _ll and _lh, 1 otherwise:
760       unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
761       RegisterCell R1 = rc(1);
762       RegisterCell R2 = rc(2);
763       RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
764       return rr0(RC, Outputs);
765     }
766     case S2_packhl: {
767       assert(W0 == 64);
768       assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
769       RegisterCell R1 = rc(1);
770       RegisterCell R2 = rc(2);
771       RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
772                                    .cat(half(R1, 1));
773       return rr0(RC, Outputs);
774     }
775     case S2_shuffeb: {
776       RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
777       return rr0(RC, Outputs);
778     }
779     case S2_shuffeh: {
780       RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
781       return rr0(RC, Outputs);
782     }
783     case S2_shuffob: {
784       RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
785       return rr0(RC, Outputs);
786     }
787     case S2_shuffoh: {
788       RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
789       return rr0(RC, Outputs);
790     }
791     case C2_mask: {
792       uint16_t WR = W0;
793       uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
794       assert(WR == 64 && WP == 8);
795       RegisterCell R1 = rc(1);
796       RegisterCell RC(WR);
797       for (uint16_t i = 0; i < WP; ++i) {
798         const BT::BitValue &V = R1[i];
799         BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
800         RC.fill(i*8, i*8+8, F);
801       }
802       return rr0(RC, Outputs);
803     }
804 
805     // Mux:
806 
807     case C2_muxii:
808     case C2_muxir:
809     case C2_muxri:
810     case C2_mux: {
811       BT::BitValue PC0 = rc(1)[0];
812       RegisterCell R2 = cop(2, W0);
813       RegisterCell R3 = cop(3, W0);
814       if (PC0.is(0) || PC0.is(1))
815         return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
816       R2.meet(R3, Reg[0].Reg);
817       return rr0(R2, Outputs);
818     }
819     case C2_vmux:
820       // TODO
821       break;
822 
823     // Sign- and zero-extension:
824 
825     case A2_sxtb:
826       return rr0(eSXT(rc(1), 8), Outputs);
827     case A2_sxth:
828       return rr0(eSXT(rc(1), 16), Outputs);
829     case A2_sxtw: {
830       uint16_t W1 = getRegBitWidth(Reg[1]);
831       assert(W0 == 64 && W1 == 32);
832       RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
833       return rr0(RC, Outputs);
834     }
835     case A2_zxtb:
836       return rr0(eZXT(rc(1), 8), Outputs);
837     case A2_zxth:
838       return rr0(eZXT(rc(1), 16), Outputs);
839 
840     // Saturations
841 
842     case A2_satb:
843       return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
844     case A2_sath:
845       return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
846     case A2_satub:
847       return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
848     case A2_satuh:
849       return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
850 
851     // Bit count:
852 
853     case S2_cl0:
854     case S2_cl0p:
855       // Always produce a 32-bit result.
856       return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
857     case S2_cl1:
858     case S2_cl1p:
859       return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
860     case S2_clb:
861     case S2_clbp: {
862       uint16_t W1 = getRegBitWidth(Reg[1]);
863       RegisterCell R1 = rc(1);
864       BT::BitValue TV = R1[W1-1];
865       if (TV.is(0) || TV.is(1))
866         return rr0(eCLB(R1, TV, 32), Outputs);
867       break;
868     }
869     case S2_ct0:
870     case S2_ct0p:
871       return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
872     case S2_ct1:
873     case S2_ct1p:
874       return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
875     case S5_popcountp:
876       // TODO
877       break;
878 
879     case C2_all8: {
880       RegisterCell P1 = rc(1);
881       bool Has0 = false, All1 = true;
882       for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
883         if (!P1[i].is(1))
884           All1 = false;
885         if (!P1[i].is(0))
886           continue;
887         Has0 = true;
888         break;
889       }
890       if (!Has0 && !All1)
891         break;
892       RegisterCell RC(W0);
893       RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
894       return rr0(RC, Outputs);
895     }
896     case C2_any8: {
897       RegisterCell P1 = rc(1);
898       bool Has1 = false, All0 = true;
899       for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
900         if (!P1[i].is(0))
901           All0 = false;
902         if (!P1[i].is(1))
903           continue;
904         Has1 = true;
905         break;
906       }
907       if (!Has1 && !All0)
908         break;
909       RegisterCell RC(W0);
910       RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
911       return rr0(RC, Outputs);
912     }
913     case C2_and:
914       return rr0(eAND(rc(1), rc(2)), Outputs);
915     case C2_andn:
916       return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
917     case C2_not:
918       return rr0(eNOT(rc(1)), Outputs);
919     case C2_or:
920       return rr0(eORL(rc(1), rc(2)), Outputs);
921     case C2_orn:
922       return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
923     case C2_xor:
924       return rr0(eXOR(rc(1), rc(2)), Outputs);
925     case C4_and_and:
926       return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
927     case C4_and_andn:
928       return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
929     case C4_and_or:
930       return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
931     case C4_and_orn:
932       return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
933     case C4_or_and:
934       return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
935     case C4_or_andn:
936       return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
937     case C4_or_or:
938       return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
939     case C4_or_orn:
940       return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
941     case C2_bitsclr:
942     case C2_bitsclri:
943     case C2_bitsset:
944     case C4_nbitsclr:
945     case C4_nbitsclri:
946     case C4_nbitsset:
947       // TODO
948       break;
949     case S2_tstbit_i:
950     case S4_ntstbit_i: {
951       BT::BitValue V = rc(1)[im(2)];
952       if (V.is(0) || V.is(1)) {
953         // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
954         bool TV = (Opc == S2_tstbit_i);
955         BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
956         return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
957       }
958       break;
959     }
960 
961     default:
962       // For instructions that define a single predicate registers, store
963       // the low 8 bits of the register only.
964       if (unsigned DefR = getUniqueDefVReg(MI)) {
965         if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
966           BT::RegisterRef PD(DefR, 0);
967           uint16_t RW = getRegBitWidth(PD);
968           uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
969           RegisterCell RC = RegisterCell::self(DefR, RW);
970           RC.fill(PW, RW, BT::BitValue::Zero);
971           putCell(PD, RC, Outputs);
972           return true;
973         }
974       }
975       return MachineEvaluator::evaluate(MI, Inputs, Outputs);
976   }
977   #undef im
978   #undef rc
979   #undef op
980   return false;
981 }
982 
evaluate(const MachineInstr & BI,const CellMapType & Inputs,BranchTargetList & Targets,bool & FallsThru) const983 bool HexagonEvaluator::evaluate(const MachineInstr &BI,
984                                 const CellMapType &Inputs,
985                                 BranchTargetList &Targets,
986                                 bool &FallsThru) const {
987   // We need to evaluate one branch at a time. TII::analyzeBranch checks
988   // all the branches in a basic block at once, so we cannot use it.
989   unsigned Opc = BI.getOpcode();
990   bool SimpleBranch = false;
991   bool Negated = false;
992   switch (Opc) {
993     case Hexagon::J2_jumpf:
994     case Hexagon::J2_jumpfpt:
995     case Hexagon::J2_jumpfnew:
996     case Hexagon::J2_jumpfnewpt:
997       Negated = true;
998       LLVM_FALLTHROUGH;
999     case Hexagon::J2_jumpt:
1000     case Hexagon::J2_jumptpt:
1001     case Hexagon::J2_jumptnew:
1002     case Hexagon::J2_jumptnewpt:
1003       // Simple branch:  if([!]Pn) jump ...
1004       // i.e. Op0 = predicate, Op1 = branch target.
1005       SimpleBranch = true;
1006       break;
1007     case Hexagon::J2_jump:
1008       Targets.insert(BI.getOperand(0).getMBB());
1009       FallsThru = false;
1010       return true;
1011     default:
1012       // If the branch is of unknown type, assume that all successors are
1013       // executable.
1014       return false;
1015   }
1016 
1017   if (!SimpleBranch)
1018     return false;
1019 
1020   // BI is a conditional branch if we got here.
1021   RegisterRef PR = BI.getOperand(0);
1022   RegisterCell PC = getCell(PR, Inputs);
1023   const BT::BitValue &Test = PC[0];
1024 
1025   // If the condition is neither true nor false, then it's unknown.
1026   if (!Test.is(0) && !Test.is(1))
1027     return false;
1028 
1029   // "Test.is(!Negated)" means "branch condition is true".
1030   if (!Test.is(!Negated)) {
1031     // Condition known to be false.
1032     FallsThru = true;
1033     return true;
1034   }
1035 
1036   Targets.insert(BI.getOperand(1).getMBB());
1037   FallsThru = false;
1038   return true;
1039 }
1040 
getUniqueDefVReg(const MachineInstr & MI) const1041 unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1042   unsigned DefReg = 0;
1043   for (const MachineOperand &Op : MI.operands()) {
1044     if (!Op.isReg() || !Op.isDef())
1045       continue;
1046     unsigned R = Op.getReg();
1047     if (!TargetRegisterInfo::isVirtualRegister(R))
1048       continue;
1049     if (DefReg != 0)
1050       return 0;
1051     DefReg = R;
1052   }
1053   return DefReg;
1054 }
1055 
evaluateLoad(const MachineInstr & MI,const CellMapType & Inputs,CellMapType & Outputs) const1056 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1057                                     const CellMapType &Inputs,
1058                                     CellMapType &Outputs) const {
1059   using namespace Hexagon;
1060 
1061   if (TII.isPredicated(MI))
1062     return false;
1063   assert(MI.mayLoad() && "A load that mayn't?");
1064   unsigned Opc = MI.getOpcode();
1065 
1066   uint16_t BitNum;
1067   bool SignEx;
1068 
1069   switch (Opc) {
1070     default:
1071       return false;
1072 
1073 #if 0
1074     // memb_fifo
1075     case L2_loadalignb_pbr:
1076     case L2_loadalignb_pcr:
1077     case L2_loadalignb_pi:
1078     // memh_fifo
1079     case L2_loadalignh_pbr:
1080     case L2_loadalignh_pcr:
1081     case L2_loadalignh_pi:
1082     // membh
1083     case L2_loadbsw2_pbr:
1084     case L2_loadbsw2_pci:
1085     case L2_loadbsw2_pcr:
1086     case L2_loadbsw2_pi:
1087     case L2_loadbsw4_pbr:
1088     case L2_loadbsw4_pci:
1089     case L2_loadbsw4_pcr:
1090     case L2_loadbsw4_pi:
1091     // memubh
1092     case L2_loadbzw2_pbr:
1093     case L2_loadbzw2_pci:
1094     case L2_loadbzw2_pcr:
1095     case L2_loadbzw2_pi:
1096     case L2_loadbzw4_pbr:
1097     case L2_loadbzw4_pci:
1098     case L2_loadbzw4_pcr:
1099     case L2_loadbzw4_pi:
1100 #endif
1101 
1102     case L2_loadrbgp:
1103     case L2_loadrb_io:
1104     case L2_loadrb_pbr:
1105     case L2_loadrb_pci:
1106     case L2_loadrb_pcr:
1107     case L2_loadrb_pi:
1108     case PS_loadrbabs:
1109     case L4_loadrb_ap:
1110     case L4_loadrb_rr:
1111     case L4_loadrb_ur:
1112       BitNum = 8;
1113       SignEx = true;
1114       break;
1115 
1116     case L2_loadrubgp:
1117     case L2_loadrub_io:
1118     case L2_loadrub_pbr:
1119     case L2_loadrub_pci:
1120     case L2_loadrub_pcr:
1121     case L2_loadrub_pi:
1122     case PS_loadrubabs:
1123     case L4_loadrub_ap:
1124     case L4_loadrub_rr:
1125     case L4_loadrub_ur:
1126       BitNum = 8;
1127       SignEx = false;
1128       break;
1129 
1130     case L2_loadrhgp:
1131     case L2_loadrh_io:
1132     case L2_loadrh_pbr:
1133     case L2_loadrh_pci:
1134     case L2_loadrh_pcr:
1135     case L2_loadrh_pi:
1136     case PS_loadrhabs:
1137     case L4_loadrh_ap:
1138     case L4_loadrh_rr:
1139     case L4_loadrh_ur:
1140       BitNum = 16;
1141       SignEx = true;
1142       break;
1143 
1144     case L2_loadruhgp:
1145     case L2_loadruh_io:
1146     case L2_loadruh_pbr:
1147     case L2_loadruh_pci:
1148     case L2_loadruh_pcr:
1149     case L2_loadruh_pi:
1150     case L4_loadruh_rr:
1151     case PS_loadruhabs:
1152     case L4_loadruh_ap:
1153     case L4_loadruh_ur:
1154       BitNum = 16;
1155       SignEx = false;
1156       break;
1157 
1158     case L2_loadrigp:
1159     case L2_loadri_io:
1160     case L2_loadri_pbr:
1161     case L2_loadri_pci:
1162     case L2_loadri_pcr:
1163     case L2_loadri_pi:
1164     case L2_loadw_locked:
1165     case PS_loadriabs:
1166     case L4_loadri_ap:
1167     case L4_loadri_rr:
1168     case L4_loadri_ur:
1169     case LDriw_pred:
1170       BitNum = 32;
1171       SignEx = true;
1172       break;
1173 
1174     case L2_loadrdgp:
1175     case L2_loadrd_io:
1176     case L2_loadrd_pbr:
1177     case L2_loadrd_pci:
1178     case L2_loadrd_pcr:
1179     case L2_loadrd_pi:
1180     case L4_loadd_locked:
1181     case PS_loadrdabs:
1182     case L4_loadrd_ap:
1183     case L4_loadrd_rr:
1184     case L4_loadrd_ur:
1185       BitNum = 64;
1186       SignEx = true;
1187       break;
1188   }
1189 
1190   const MachineOperand &MD = MI.getOperand(0);
1191   assert(MD.isReg() && MD.isDef());
1192   RegisterRef RD = MD;
1193 
1194   uint16_t W = getRegBitWidth(RD);
1195   assert(W >= BitNum && BitNum > 0);
1196   RegisterCell Res(W);
1197 
1198   for (uint16_t i = 0; i < BitNum; ++i)
1199     Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1200 
1201   if (SignEx) {
1202     const BT::BitValue &Sign = Res[BitNum-1];
1203     for (uint16_t i = BitNum; i < W; ++i)
1204       Res[i] = BT::BitValue::ref(Sign);
1205   } else {
1206     for (uint16_t i = BitNum; i < W; ++i)
1207       Res[i] = BT::BitValue::Zero;
1208   }
1209 
1210   putCell(RD, Res, Outputs);
1211   return true;
1212 }
1213 
evaluateFormalCopy(const MachineInstr & MI,const CellMapType & Inputs,CellMapType & Outputs) const1214 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1215                                           const CellMapType &Inputs,
1216                                           CellMapType &Outputs) const {
1217   // If MI defines a formal parameter, but is not a copy (loads are handled
1218   // in evaluateLoad), then it's not clear what to do.
1219   assert(MI.isCopy());
1220 
1221   RegisterRef RD = MI.getOperand(0);
1222   RegisterRef RS = MI.getOperand(1);
1223   assert(RD.Sub == 0);
1224   if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
1225     return false;
1226   RegExtMap::const_iterator F = VRX.find(RD.Reg);
1227   if (F == VRX.end())
1228     return false;
1229 
1230   uint16_t EW = F->second.Width;
1231   // Store RD's cell into the map. This will associate the cell with a virtual
1232   // register, and make zero-/sign-extends possible (otherwise we would be ex-
1233   // tending "self" bit values, which will have no effect, since "self" values
1234   // cannot be references to anything).
1235   putCell(RD, getCell(RS, Inputs), Outputs);
1236 
1237   RegisterCell Res;
1238   // Read RD's cell from the outputs instead of RS's cell from the inputs:
1239   if (F->second.Type == ExtType::SExt)
1240     Res = eSXT(getCell(RD, Outputs), EW);
1241   else if (F->second.Type == ExtType::ZExt)
1242     Res = eZXT(getCell(RD, Outputs), EW);
1243 
1244   putCell(RD, Res, Outputs);
1245   return true;
1246 }
1247 
getNextPhysReg(unsigned PReg,unsigned Width) const1248 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1249   using namespace Hexagon;
1250 
1251   bool Is64 = DoubleRegsRegClass.contains(PReg);
1252   assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1253 
1254   static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1255   static const unsigned Phys64[] = { D0, D1, D2 };
1256   const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1257   const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1258 
1259   // Return the first parameter register of the required width.
1260   if (PReg == 0)
1261     return (Width <= 32) ? Phys32[0] : Phys64[0];
1262 
1263   // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1264   // next register.
1265   unsigned Idx32 = 0, Idx64 = 0;
1266   if (!Is64) {
1267     while (Idx32 < Num32) {
1268       if (Phys32[Idx32] == PReg)
1269         break;
1270       Idx32++;
1271     }
1272     Idx64 = Idx32/2;
1273   } else {
1274     while (Idx64 < Num64) {
1275       if (Phys64[Idx64] == PReg)
1276         break;
1277       Idx64++;
1278     }
1279     Idx32 = Idx64*2+1;
1280   }
1281 
1282   if (Width <= 32)
1283     return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1284   return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1285 }
1286 
getVirtRegFor(unsigned PReg) const1287 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1288   for (std::pair<unsigned,unsigned> P : MRI.liveins())
1289     if (P.first == PReg)
1290       return P.second;
1291   return 0;
1292 }
1293