Home
last modified time | relevance | path

Searched refs:getReg (Results 1 – 25 of 486) sorted by relevance

12345678910>>...20

/freebsd-12.1/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp277 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
288 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
299 AccName = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
310 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
322 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
334 AccName = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
346 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
370 AccName = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
408 AccName = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
439 AccName = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
88 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
90 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
98 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
100 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
121 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
122 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
130 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
131 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp123 unsigned Def = MI->getOperand(0).getReg(); in trackCopy()
124 unsigned Src = MI->getOperand(1).getReg(); in trackCopy()
362 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
389 if (!MOUse.getReg()) in forwardUses()
404 unsigned CopySrcReg = CopySrc.getReg(); in forwardUses()
407 if (MOUse.getReg() != CopyDstReg) { in forwardUses()
488 Src = MI->getOperand(1).getReg(); in CopyPropagateBlock()
496 unsigned Reg = MO.getReg(); in CopyPropagateBlock()
519 unsigned Reg = MO.getReg(); in CopyPropagateBlock()
533 unsigned Reg = MO.getReg(); in CopyPropagateBlock()
[all …]
H A DTwoAddressInstructionPass.cpp234 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
238 UseRegs.insert(MO.getReg()); in sink3AddrInstruction()
247 DefReg = MO.getReg(); in sink3AddrInstruction()
303 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
915 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill()
959 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill()
1097 unsigned MOReg = MO.getReg(); in rescheduleKillAboveMI()
1134 unsigned MOReg = MO.getReg(); in rescheduleKillAboveMI()
1473 unsigned SrcReg = SrcMO.getReg(); in collectTiedOperands()
1474 unsigned DstReg = DstMO.getReg(); in collectTiedOperands()
[all …]
H A DLiveRangeShrink.cpp145 UseMap[MO.getReg()] = std::make_pair(CurrentOrder, &MI); in runOnMachineFunction()
146 else if (MO.isDead() && UseMap.count(MO.getReg())) in runOnMachineFunction()
149 if (Barrier < UseMap[MO.getReg()].first) { in runOnMachineFunction()
150 Barrier = UseMap[MO.getReg()].first; in runOnMachineFunction()
151 BarrierMI = UseMap[MO.getReg()].second; in runOnMachineFunction()
176 unsigned Reg = MO.getReg(); in runOnMachineFunction()
193 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
194 MRI.getRegClass(MO.getReg())) { in runOnMachineFunction()
238 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg(); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp98 printRegName(O, Dst.getReg()); in printInst()
100 printRegName(O, MO1.getReg()); in printInst()
103 printRegName(O, MO2.getReg()); in printInst()
120 printRegName(O, Dst.getReg()); in printInst()
303 unsigned Reg = Op.getReg(); in printOperand()
416 if (!MO2.getReg()) { in printAM2PreOrOffsetIndexOp()
485 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
514 if (MO2.getReg()) { in printAM3PreOrOffsetIndexOp()
555 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
683 if (MO.getReg() == 0) in printAddrMode6OffsetOperand()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp643 MO.setReg(ExtB->getOperand(0).getReg()); in widenScalarSrc()
982 .addUse(MI.getOperand(1).getReg()) in lower()
983 .addUse(MI.getOperand(2).getReg()); in lower()
987 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), in lower()
996 unsigned Res = MI.getOperand(0).getReg(); in lower()
998 unsigned LHS = MI.getOperand(2).getReg(); in lower()
999 unsigned RHS = MI.getOperand(3).getReg(); in lower()
1038 unsigned Res = MI.getOperand(0).getReg(); in lower()
1062 .addUse(Zero->getOperand(0).getReg()) in lower()
1063 .addUse(MI.getOperand(1).getReg()); in lower()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp58 const MachineInstr *Def = MRI.getVRegDef(MO.getReg()); in isConstant()
112 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
141 unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
177 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
262 unsigned Reg = MI.getOperand(i).getReg(); in isSALUMapping()
302 unsigned Reg1 = MI.getOperand(OpdIdx).getReg(); in getDefaultMappingVOP()
342 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrMappingForLoad()
505 unsigned Dst = MI.getOperand(0).getReg(); in getInstrMapping()
506 unsigned Src = MI.getOperand(1).getReg(); in getInstrMapping()
517 unsigned Dst = MI.getOperand(0).getReg(); in getInstrMapping()
[all …]
H A DSIShrinkInstructions.cpp79 unsigned Reg = Src0.getReg(); in foldImmediates()
270 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
271 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
275 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
304 } else if (MO.getReg() == Reg && in instAccessReg()
365 unsigned T = MovT.getOperand(0).getReg(); in matchSwap()
371 unsigned X = Xop.getReg(); in matchSwap()
550 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
551 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
555 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { in runOnMachineFunction()
[all …]
H A DAMDGPUInstructionSelector.cpp76 RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); in selectCOPY()
93 unsigned Reg = MO.getReg(); in getSubOperand64()
262 unsigned Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS()
263 unsigned Reg1 = I.getOperand(4).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS()
335 unsigned DstReg = I.getOperand(0).getReg(); in selectG_CONSTANT()
417 GEPInfo.SgprParts.push_back(GEPOp.getReg()); in getAddrModeInfo()
419 GEPInfo.VgprParts.push_back(GEPOp.getReg()); in getAddrModeInfo()
522 unsigned DstReg = I.getOperand(0).getReg(); in selectSMRD()
567 unsigned PtrReg = I.getOperand(1).getReg(); in selectSMRD()
582 unsigned DstReg = I.getOperand(0).getReg(); in selectG_LOAD()
[all …]
H A DSIFoldOperands.cpp451 unsigned DestReg = UseMI->getOperand(0).getReg(); in foldOperand()
457 unsigned SrcReg = UseMI->getOperand(1).getReg(); in foldOperand()
495 UseMI->getOperand(1).setReg(OpToFold.getReg()); in foldOperand()
530 unsigned UseReg = UseOp.getReg(); in foldOperand()
638 MachineInstr *Def = MRI.getVRegDef(Op.getReg()); in getImmOrMaterializedImm()
830 NextUse = MRI->use_begin(Dst.getReg()); in foldInstOperand()
922 Src0->getReg() != Src1->getReg() || in isClamp()
982 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); in tryFoldClamp()
1066 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() && in isOMod()
1088 !hasOneNonDBGUseInst(*MRI, RegOp->getReg())) in tryFoldOMod()
[all …]
H A DSIOptimizeExecMasking.cpp66 if (Src.isReg() && Src.getReg() == AMDGPU::EXEC) in isCopyFromExec()
67 return MI.getOperand(0).getReg(); in isCopyFromExec()
81 return MI.getOperand(1).getReg(); in isCopyToExec()
104 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
105 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
107 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
108 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
265 unsigned CopyFromExec = CopyFromExecInst->getOperand(0).getReg(); in runOnMachineFunction()
333 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
335 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h43 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
76 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
105 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
141 unsigned DstReg = MI.getOperand(0).getReg(); in tryFoldImplicitDef()
174 LLT OpTy = MRI.getType(MI.getOperand(NumDefs).getReg()); in tryCombineMerges()
175 LLT DestTy = MRI.getType(MI.getOperand(0).getReg()); in tryCombineMerges()
208 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineMerges()
230 Regs.push_back(MergeI->getOperand(Idx).getReg()); in tryCombineMerges()
238 if (MRI.getType(MI.getOperand(0).getReg()) != in tryCombineMerges()
239 MRI.getType(MergeI->getOperand(1).getReg())) in tryCombineMerges()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp203 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
204 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
221 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
222 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
242 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
243 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
252 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
253 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
262 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
263 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp132 unsigned Reg = Op->getReg(); in getVRegDefOrNull()
331 MI.getOperand(0).getReg()) in simplifyCode()
352 MI.getOperand(0).getReg()) in simplifyCode()
377 MI.getOperand(0).getReg()) in simplifyCode()
433 MI.getOperand(0).getReg()) in simplifyCode()
617 MI.getOperand(0).getReg()) in simplifyCode()
664 MI.getOperand(0).getReg()) in simplifyCode()
717 unsigned DominatorReg = Op2.getReg(); in simplifyCode()
754 MI.getOperand(0).getReg()) in simplifyCode()
856 return Phi->getOperand(I-1).getReg(); in getIncomingRegForBlock()
[all …]
H A DPPCVSXCopy.cpp99 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
100 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
105 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
106 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
107 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
120 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
121 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
126 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
127 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
128 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp261 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
274 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
281 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
347 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
349 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
361 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
371 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
373 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
374 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); in getInstrMapping()
393 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
[all …]
H A DA15SDOptimizer.cpp137 unsigned Reg = MO.getReg(); in usesRegClass()
167 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
195 unsigned Reg = MO.getReg(); in eraseInstrWithNoUses()
217 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses()
249 unsigned DPRReg = MI->getOperand(1).getReg(); in optimizeSDPattern()
250 unsigned SPRReg = MI->getOperand(2).getReg(); in optimizeSDPattern()
300 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern()
311 NonImplicitReg = MI->getOperand(I).getReg(); in optimizeSDPattern()
373 unsigned Reg = MI->getOperand(I).getReg(); in elideCopiesAndPHIs()
412 Defs.push_back(MO.getReg()); in getReadDPRs()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp214 unsigned R = Op.getReg(); in isFixedInstr()
262 unsigned T = MO.getReg(); in partitionRegisters()
503 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
539 unsigned R = MD.getReg(); in collectIndRegsForLoop()
607 unsigned R = Op.getReg(); in createHalfInstr()
681 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
814 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
950 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
964 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
1083 unsigned R = Op.getReg(); in replaceSubregUses()
[all …]
H A DHexagonPeephole.cpp140 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
141 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
161 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
162 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
178 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
179 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
189 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
190 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
212 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
213 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
[all …]
H A DHexagonInstrInfo.cpp197 unsigned Reg = MO.getReg(); in parseOperands()
1039 if (MD.getReg() != MS.getReg() && !MS.isUndef()) { in expandPostRAPseudo()
1040 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill()); in expandPostRAPseudo()
1254 if (Op0.getReg() != Op2.getReg()) { in expandPostRAPseudo()
1255 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1265 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1288 if (Op0.getReg() != Op2.getReg()) { in expandPostRAPseudo()
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1302 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
2583 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp190 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
356 unsigned DstReg = I.getOperand(0).getReg(); in selectCopy()
357 unsigned SrcReg = I.getOperand(1).getReg(); in selectCopy()
606 unsigned LHS = CCMI->getOperand(2).getReg(); in selectCompareBranch()
607 unsigned RHS = CCMI->getOperand(3).getReg(); in selectCompareBranch()
649 unsigned ListReg = I.getOperand(0).getReg(); in selectVaStartDarwin()
942 .addDef(I.getOperand(0).getReg()) in select()
977 .addUse(I.getOperand(2).getReg()) in select()
1363 MRI.getType(I.getOperand(1).getReg())) in select()
1630 .addDef(I.getOperand(0).getReg()) in selectMergeValues()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1530 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
1552 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemEVA()
1574 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte15()
1805 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMSPImm5Lsl2()
1821 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMGPImm7Lsl2()
1863 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm9()
1973 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMem2()
1991 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); in DecodeFMem3()
2009 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2R6()
2025 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2MMR6()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp87 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in detectLuiAddiGlobal()
89 unsigned HiLuiDestReg = HiLUI.getOperand(0).getReg(); in detectLuiAddiGlobal()
95 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) in detectLuiAddiGlobal()
111 MRI->replaceRegWith(Tail.getOperand(0).getReg(), in foldOffset()
112 LoADDI.getOperand(0).getReg()); in foldOffset()
139 unsigned Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset()
140 unsigned Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset()
156 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); in matchLargeOffset()
160 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg())) in matchLargeOffset()
182 unsigned DestReg = LoADDI.getOperand(0).getReg(); in detectAndFoldOffset()
[all …]
H A DRISCVExpandPseudoInsts.cpp161 unsigned DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion()
163 unsigned AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion()
164 unsigned IncrReg = MI.getOperand(3).getReg(); in doAtomicBinOpExpansion()
223 unsigned DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion()
225 unsigned AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion()
226 unsigned IncrReg = MI.getOperand(3).getReg(); in doMaskedAtomicBinOpExpansion()
227 unsigned MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion()
362 unsigned DestReg = MI.getOperand(0).getReg(); in expandAtomicMinMaxOp()
365 unsigned AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp()
366 unsigned IncrReg = MI.getOperand(4).getReg(); in expandAtomicMinMaxOp()
[all …]

12345678910>>...20