Lines Matching refs:getReg
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
88 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
90 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
97 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorStore()
98 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
100 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
121 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
122 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
130 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
131 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
139 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
148 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
157 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
158 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
166 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
167 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
175 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
184 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
200 .addReg(MI->getOperand(0).getReg()); in EmitInstruction()
228 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
229 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
237 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
238 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
246 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
255 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
264 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
265 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
273 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
274 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
282 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
291 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
314 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
320 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in EmitInstruction()
326 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in EmitInstruction()
342 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
343 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg())) in EmitInstruction()
344 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); in EmitInstruction()
350 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in EmitInstruction()
351 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())); in EmitInstruction()
372 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg())) in EmitInstruction()
373 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())) in EmitInstruction()
379 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in EmitInstruction()
380 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in EmitInstruction()
381 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
556 ScratchReg = MI.getOperand(ScratchIdx).getReg(); in LowerPATCHPOINT()
643 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), in PrintAsmMemoryOperand()
645 MI->getOperand(OpNo + 2).getReg(), OS); in PrintAsmMemoryOperand()