Lines Matching refs:getReg
197 unsigned Reg = MO.getReg(); in parseOperands()
202 Uses.push_back(MO.getReg()); in parseOperands()
205 Defs.push_back(MO.getReg()); in parseOperands()
262 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
276 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
310 return MI.getOperand(2).getReg(); in isStoreToStackSlot()
328 return MI.getOperand(3).getReg(); in isStoreToStackSlot()
636 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
637 addReg(Cond[2].getReg(), Flags2).addMBB(TBB); in insertBranch()
639 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
647 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); in insertBranch()
671 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); in insertBranch()
731 unsigned LoopCount = Loop->getOperand(1).getReg(); in reduceLoopCount()
1021 unsigned Mx = MI.getOperand(MxOp).getReg(); in expandPostRAPseudo()
1039 if (MD.getReg() != MS.getReg() && !MS.isUndef()) { in expandPostRAPseudo()
1040 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill()); in expandPostRAPseudo()
1047 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1053 unsigned SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1054 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1063 unsigned SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1064 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1072 unsigned SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1073 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1083 unsigned SrcReg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1107 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1126 unsigned Reg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1134 unsigned Reg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1142 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1149 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1156 unsigned Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1165 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1166 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1167 unsigned Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1189 unsigned DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1190 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1191 unsigned Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1192 unsigned Src3Reg = MI.getOperand(3).getReg(); in expandPostRAPseudo()
1223 unsigned Rd = Op0.getReg(); in expandPostRAPseudo()
1224 unsigned Pu = Op1.getReg(); in expandPostRAPseudo()
1225 unsigned Rs = Op2.getReg(); in expandPostRAPseudo()
1226 unsigned Rt = Op3.getReg(); in expandPostRAPseudo()
1249 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); in expandPostRAPseudo()
1250 unsigned PReg = Op1.getReg(); in expandPostRAPseudo()
1254 if (Op0.getReg() != Op2.getReg()) { in expandPostRAPseudo()
1255 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1262 T.addReg(Op0.getReg(), RegState::Implicit); in expandPostRAPseudo()
1265 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1271 T.addReg(Op0.getReg(), RegState::Implicit); in expandPostRAPseudo()
1283 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); in expandPostRAPseudo()
1284 unsigned PReg = Op1.getReg(); in expandPostRAPseudo()
1288 if (Op0.getReg() != Op2.getReg()) { in expandPostRAPseudo()
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1291 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1292 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1299 T.addReg(Op0.getReg(), RegState::Implicit); in expandPostRAPseudo()
1302 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1303 unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1304 unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1311 T.addReg(Op0.getReg(), RegState::Implicit); in expandPostRAPseudo()
1585 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); in DefinesPredicate()
1742 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1751 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1760 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1782 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1841 unsigned BaseRegA = BaseA.getReg(); in areMemAccessesTriviallyDisjoint()
1849 unsigned BaseRegB = BaseB.getReg(); in areMemAccessesTriviallyDisjoint()
2574 unsigned DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2577 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2583 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
2912 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29) in canExecuteInBundle()
2926 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg()) in canExecuteInBundle()
3058 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
3264 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3265 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3266 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
3276 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3277 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3287 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3288 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3296 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3301 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3302 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3317 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3343 unsigned DestReg = GA.getOperand(0).getReg(); in getCompoundOpcode()
3694 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3695 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3713 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3714 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3732 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3733 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3741 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3742 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3750 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3751 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3771 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3784 DstReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3785 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3799 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3811 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3812 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
3826 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3827 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
3843 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3844 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
3852 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3853 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
3862 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3870 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3900 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3901 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3922 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3923 Src1Reg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3924 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
3933 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3934 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3943 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3944 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3953 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3964 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3965 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3973 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3974 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3983 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3995 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3996 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4004 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4005 SrcReg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4016 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4017 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4060 if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) { in getOperandLatency()
4062 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
4073 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
4225 PredReg = Cond[1].getReg(); in getPredReg()