Lines Matching refs:getReg
234 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
238 UseRegs.insert(MO.getReg()); in sink3AddrInstruction()
247 DefReg = MO.getReg(); in sink3AddrInstruction()
303 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
373 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
414 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
415 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
417 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
418 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
507 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
511 DstReg = MI.getOperand(ti).getReg(); in isTwoAddrUse()
687 unsigned RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction()
704 unsigned RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
915 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill()
934 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) in rescheduleMIBelowKill()
935 Defs.push_back(End->getOperand(0).getReg()); in rescheduleMIBelowKill()
959 unsigned MOReg = MO.getReg(); in rescheduleMIBelowKill()
1097 unsigned MOReg = MO.getReg(); in rescheduleKillAboveMI()
1134 unsigned MOReg = MO.getReg(); in rescheduleKillAboveMI()
1212 unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg(); in tryInstructionCommute()
1213 unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg(); in tryInstructionCommute()
1225 unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); in tryInstructionCommute()
1275 unsigned regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1276 unsigned regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1311 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1399 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { in tryInstructionTransform()
1402 if (NewMIs[0]->killsRegister(MO.getReg())) in tryInstructionTransform()
1403 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]); in tryInstructionTransform()
1405 assert(NewMIs[1]->killsRegister(MO.getReg()) && in tryInstructionTransform()
1407 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]); in tryInstructionTransform()
1410 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) { in tryInstructionTransform()
1411 if (NewMIs[1]->registerDefIsDead(MO.getReg())) in tryInstructionTransform()
1412 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]); in tryInstructionTransform()
1414 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && in tryInstructionTransform()
1416 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]); in tryInstructionTransform()
1428 OrigRegs.push_back(MO.getReg()); in tryInstructionTransform()
1473 unsigned SrcReg = SrcMO.getReg(); in collectTiedOperands()
1474 unsigned DstReg = DstMO.getReg(); in collectTiedOperands()
1521 unsigned RegA = DstMO.getReg(); in processTiedPairs()
1525 RegB = MI->getOperand(SrcIdx).getReg(); in processTiedPairs()
1547 MI->getOperand(i).getReg() != RegA); in processTiedPairs()
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1618 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1658 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1743 unsigned SrcReg = mi->getOperand(SrcIdx).getReg(); in runOnMachineFunction()
1744 unsigned DstReg = mi->getOperand(DstIdx).getReg(); in runOnMachineFunction()
1802 unsigned DstReg = MI.getOperand(0).getReg(); in eliminateRegSequence()
1812 OrigRegs.push_back(MI.getOperand(0).getReg()); in eliminateRegSequence()
1814 OrigRegs.push_back(MI.getOperand(i).getReg()); in eliminateRegSequence()
1820 unsigned SrcReg = UseMO.getReg(); in eliminateRegSequence()
1831 if (MI.getOperand(j).getReg() == SrcReg) { in eliminateRegSequence()