Lines Matching refs:getReg
214 unsigned R = Op.getReg(); in isFixedInstr()
262 unsigned T = MO.getReg(); in partitionRegisters()
376 unsigned Rs = MI->getOperand(1).getReg(); in profit()
377 unsigned Rt = MI->getOperand(2).getReg(); in profit()
444 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
503 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
511 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
539 unsigned R = MD.getReg(); in collectIndRegsForLoop()
555 unsigned T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
607 unsigned R = Op.getReg(); in createHalfInstr()
647 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
654 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
657 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
663 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
667 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
677 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
681 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
683 MRI->replaceRegWith(UpdOp.getReg(), NewR); in splitMemRef()
710 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitImmediate()
737 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitCombine()
746 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
754 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
766 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitExt()
772 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
774 .addReg(Op1.getReg(), RS, Op1.getSubReg()) in splitExt()
790 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitShift()
812 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
814 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
837 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
840 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
843 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
849 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift()
855 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
860 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR) in splitShift()
865 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
871 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)); in splitShift()
877 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
883 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift()
886 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR); in splitShift()
889 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)) in splitShift()
894 .addReg(Op1.getReg(), RS, HiSR) in splitShift()
915 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); in splitAslOr()
947 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
948 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
950 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
951 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
954 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
955 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
959 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
964 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
968 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
976 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
978 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
979 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
987 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
989 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
990 .addReg(Op2.getReg(), RS2, LoSR) in splitAslOr()
1006 unsigned DstR = MI->getOperand(0).getReg(); in splitInstr()
1083 unsigned R = Op.getReg(); in replaceSubregUses()
1108 unsigned R = Op.getReg(); in collapseRegPairs()