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Searched refs:getLocVT (Results 1 – 25 of 29) sorted by relevance

12

/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp240 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
451 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
453 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
852 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
903 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
989 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
1050 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1160 || VA.getLocVT() != MVT::i128) in LowerCall_64()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp274 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
277 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
280 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
486 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
503 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerCallArguments()
512 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCallArguments()
642 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerReturn()
670 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86CallLowering.cpp138 unsigned LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
153 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
269 unsigned LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
282 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
H A DX86FastISel.cpp3344 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3353 ArgVT = VA.getLocVT(); in fastLowerCall()
3357 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3373 ArgVT = VA.getLocVT(); in fastLowerCall()
3377 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3379 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3382 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3385 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3389 ArgVT = VA.getLocVT(); in fastLowerCall()
3393 ArgReg = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg, in fastLowerCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
262 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
337 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
340 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
343 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp137 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
255 LLT LocTy{VA.getLocVT()}; in extendRegister()
324 VA.getLocMemOffset(), VA.getLocVT(), LocInfo); in setLocInfo()
327 VA.getLocReg(), VA.getLocVT(), LocInfo); in setLocInfo()
H A DMipsISelLowering.cpp3049 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
3121 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
3123 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
3284 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
3288 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
3327 MVT LocVT = VA.getLocVT(); in UnpackFromArgumentSlot()
3338 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in UnpackFromArgumentSlot()
3342 Opcode, DL, VA.getLocVT(), Val, in UnpackFromArgumentSlot()
3443 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
3473 MVT LocVT = VA.getLocVT(); in LowerFormalArguments()
[all …]
H A DMipsFastISel.cpp1207 MVT DestVT = VA.getLocVT(); in processCallArgs()
1215 MVT DestVT = VA.getLocVT(); in processCallArgs()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp773 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
780 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
994 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
1009 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
1029 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
1054 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && in unpackF64OnRV32DSoftABI()
1135 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) in LowerFormalArguments()
1387 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
1544 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { in LowerCall()
1602 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { in LowerReturn()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
492 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
496 << EVT(VA.getLocVT()).getEVTString() << "\n"; in LowerCCCArguments()
505 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
561 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
673 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp120 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
134 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
356 auto LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
H A DARMCallingConv.h188 assert(PendingMembers[0].getLocVT() == LocVT); in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMFastISel.cpp1924 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1974 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1983 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1990 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, in ProcessCallArgs()
1994 ArgVT = VA.getLocVT(); in ProcessCallArgs()
2007 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
H A DARMISelLowering.cpp1688 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1710 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1880 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1883 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1889 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1915 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
2379 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
2521 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2526 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
3670 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp625 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
668 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
671 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
681 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
753 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
819 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
822 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
825 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp80 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
159 Size = VA.getLocVT().getSizeInBits() / 8; in assignValueToAddress()
H A DAArch64ISelLowering.cpp3079 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
3149 MemVT = VA.getLocVT(); in LowerFormalArguments()
3163 ExtType, DL, VA.getLocVT(), Chain, FIN, in LowerFormalArguments()
3334 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 && in LowerCallResult()
3681 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3684 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3692 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3695 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall()
3698 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3705 assert(VA.getLocVT() == MVT::i64 && in LowerCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1144 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1147 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1150 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1295 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1315 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1318 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
1329 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1472 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerReturn()
1500 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp160 LLT LocTy{VA.getLocVT()}; in extendRegister()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp222 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
397 Arg = DAG.getBitcast(VA.getLocVT(), Arg); in LowerCall()
400 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
403 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
406 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
417 VA.getLocVT().getStoreSizeInBits() >> 3); in LowerCall()
734 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
767 : VA.getLocVT().getStoreSizeInBits() / 8; in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h152 MVT getLocVT() const { return LocVT; } in getLocVT() function
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1071 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1115 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
1200 EVT RegVT = VA.getLocVT(); in LowerCall()
1410 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1045 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1048 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1056 assert(VA.getLocVT() == MVT::i64); in convertLocVTToValVT()
1072 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1076 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1080 assert(VA.getLocVT() == MVT::i64); in convertValVTToLocVT()
1119 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
1167 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerFormalArguments()
1340 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerCall()
1424 VA.getLocVT(), Glue); in LowerCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1403 MemVT = VA.getLocVT(); in lowerStackParameter()
1417 ExtType, SL, VA.getLocVT(), Chain, FIN, in lowerStackParameter()
1966 MVT VT = VA.getLocVT(); in LowerFormalArguments()
1970 EVT MemVT = VA.getLocVT(); in LowerFormalArguments()
2158 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerReturn()
2167 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
2240 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
2245 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
2576 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall()
2585 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1443 MVT DestVT = VA.getLocVT(); in processCallArgs()
1455 MVT DestVT = VA.getLocVT(); in processCallArgs()
1759 MVT DestVT = VA.getLocVT(); in SelectRet()

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