1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
27 #include "llvm/CodeGen/GlobalISel/Utils.h"
28 #include "llvm/CodeGen/LowLevelType.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/MC/MCRegisterInfo.h"
44 #include "llvm/Support/LowLevelTypeImpl.h"
45 #include "llvm/Support/MachineValueType.h"
46 #include <cassert>
47 #include <cstdint>
48
49 using namespace llvm;
50
51 #include "X86GenCallingConv.inc"
52
X86CallLowering(const X86TargetLowering & TLI)53 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
54 : CallLowering(&TLI) {}
55
splitToValueTypes(const ArgInfo & OrigArg,SmallVectorImpl<ArgInfo> & SplitArgs,const DataLayout & DL,MachineRegisterInfo & MRI,SplitArgTy PerformArgSplit) const56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57 SmallVectorImpl<ArgInfo> &SplitArgs,
58 const DataLayout &DL,
59 MachineRegisterInfo &MRI,
60 SplitArgTy PerformArgSplit) const {
61 const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62 LLVMContext &Context = OrigArg.Ty->getContext();
63
64 SmallVector<EVT, 4> SplitVTs;
65 SmallVector<uint64_t, 4> Offsets;
66 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
67
68 if (OrigArg.Ty->isVoidTy())
69 return true;
70
71 EVT VT = SplitVTs[0];
72 unsigned NumParts = TLI.getNumRegisters(Context, VT);
73
74 if (NumParts == 1) {
75 // replace the original type ( pointer -> GPR ).
76 SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
77 OrigArg.Flags, OrigArg.IsFixed);
78 return true;
79 }
80
81 SmallVector<unsigned, 8> SplitRegs;
82
83 EVT PartVT = TLI.getRegisterType(Context, VT);
84 Type *PartTy = PartVT.getTypeForEVT(Context);
85
86 for (unsigned i = 0; i < NumParts; ++i) {
87 ArgInfo Info =
88 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
89 PartTy, OrigArg.Flags};
90 SplitArgs.push_back(Info);
91 SplitRegs.push_back(Info.Reg);
92 }
93
94 PerformArgSplit(SplitRegs);
95 return true;
96 }
97
98 namespace {
99
100 struct OutgoingValueHandler : public CallLowering::ValueHandler {
OutgoingValueHandler__anon7934bec90111::OutgoingValueHandler101 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
102 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
103 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
104 DL(MIRBuilder.getMF().getDataLayout()),
105 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
106
getStackAddress__anon7934bec90111::OutgoingValueHandler107 unsigned getStackAddress(uint64_t Size, int64_t Offset,
108 MachinePointerInfo &MPO) override {
109 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
110 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
111 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
113
114 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
115 MIRBuilder.buildConstant(OffsetReg, Offset);
116
117 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
118 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
119
120 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
121 return AddrReg;
122 }
123
assignValueToReg__anon7934bec90111::OutgoingValueHandler124 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
125 CCValAssign &VA) override {
126 MIB.addUse(PhysReg, RegState::Implicit);
127
128 unsigned ExtReg;
129 // If we are copying the value to a physical register with the
130 // size larger than the size of the value itself - build AnyExt
131 // to the size of the register first and only then do the copy.
132 // The example of that would be copying from s32 to xmm0, for which
133 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
134 // we expect normal extendRegister mechanism to work.
135 unsigned PhysRegSize =
136 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
137 unsigned ValSize = VA.getValVT().getSizeInBits();
138 unsigned LocSize = VA.getLocVT().getSizeInBits();
139 if (PhysRegSize > ValSize && LocSize == ValSize) {
140 assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
142 ExtReg = MIB->getOperand(0).getReg();
143 } else
144 ExtReg = extendRegister(ValVReg, VA);
145
146 MIRBuilder.buildCopy(PhysReg, ExtReg);
147 }
148
assignValueToAddress__anon7934bec90111::OutgoingValueHandler149 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
150 MachinePointerInfo &MPO, CCValAssign &VA) override {
151 unsigned ExtReg = extendRegister(ValVReg, VA);
152 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
153 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
154 /* Alignment */ 0);
155 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
156 }
157
assignArg__anon7934bec90111::OutgoingValueHandler158 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
159 CCValAssign::LocInfo LocInfo,
160 const CallLowering::ArgInfo &Info, CCState &State) override {
161 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
162 StackSize = State.getNextStackOffset();
163
164 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
165 X86::XMM3, X86::XMM4, X86::XMM5,
166 X86::XMM6, X86::XMM7};
167 if (!Info.IsFixed)
168 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
169
170 return Res;
171 }
172
getStackSize__anon7934bec90111::OutgoingValueHandler173 uint64_t getStackSize() { return StackSize; }
getNumXmmRegs__anon7934bec90111::OutgoingValueHandler174 uint64_t getNumXmmRegs() { return NumXMMRegs; }
175
176 protected:
177 MachineInstrBuilder &MIB;
178 uint64_t StackSize = 0;
179 const DataLayout &DL;
180 const X86Subtarget &STI;
181 unsigned NumXMMRegs = 0;
182 };
183
184 } // end anonymous namespace
185
lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<unsigned> VRegs) const186 bool X86CallLowering::lowerReturn(
187 MachineIRBuilder &MIRBuilder, const Value *Val,
188 ArrayRef<unsigned> VRegs) const {
189 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
190 "Return value without a vreg");
191 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
192
193 if (!VRegs.empty()) {
194 MachineFunction &MF = MIRBuilder.getMF();
195 const Function &F = MF.getFunction();
196 MachineRegisterInfo &MRI = MF.getRegInfo();
197 auto &DL = MF.getDataLayout();
198 LLVMContext &Ctx = Val->getType()->getContext();
199 const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
200
201 SmallVector<EVT, 4> SplitEVTs;
202 ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
203 assert(VRegs.size() == SplitEVTs.size() &&
204 "For each split Type there should be exactly one VReg.");
205
206 SmallVector<ArgInfo, 8> SplitArgs;
207 for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
208 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
209 setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
210 if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
211 [&](ArrayRef<unsigned> Regs) {
212 MIRBuilder.buildUnmerge(Regs, VRegs[i]);
213 }))
214 return false;
215 }
216
217 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
218 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
219 return false;
220 }
221
222 MIRBuilder.insertInstr(MIB);
223 return true;
224 }
225
226 namespace {
227
228 struct IncomingValueHandler : public CallLowering::ValueHandler {
IncomingValueHandler__anon7934bec90311::IncomingValueHandler229 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
230 CCAssignFn *AssignFn)
231 : ValueHandler(MIRBuilder, MRI, AssignFn),
232 DL(MIRBuilder.getMF().getDataLayout()) {}
233
getStackAddress__anon7934bec90311::IncomingValueHandler234 unsigned getStackAddress(uint64_t Size, int64_t Offset,
235 MachinePointerInfo &MPO) override {
236 auto &MFI = MIRBuilder.getMF().getFrameInfo();
237 int FI = MFI.CreateFixedObject(Size, Offset, true);
238 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
239
240 unsigned AddrReg = MRI.createGenericVirtualRegister(
241 LLT::pointer(0, DL.getPointerSizeInBits(0)));
242 MIRBuilder.buildFrameIndex(AddrReg, FI);
243 return AddrReg;
244 }
245
assignValueToAddress__anon7934bec90311::IncomingValueHandler246 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
247 MachinePointerInfo &MPO, CCValAssign &VA) override {
248 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
249 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
250 0);
251 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
252 }
253
assignValueToReg__anon7934bec90311::IncomingValueHandler254 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
255 CCValAssign &VA) override {
256 markPhysRegUsed(PhysReg);
257
258 switch (VA.getLocInfo()) {
259 default: {
260 // If we are copying the value from a physical register with the
261 // size larger than the size of the value itself - build the copy
262 // of the phys reg first and then build the truncation of that copy.
263 // The example of that would be copying from xmm0 to s32, for which
264 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
265 // we expect this to be handled in SExt/ZExt/AExt case.
266 unsigned PhysRegSize =
267 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
268 unsigned ValSize = VA.getValVT().getSizeInBits();
269 unsigned LocSize = VA.getLocVT().getSizeInBits();
270 if (PhysRegSize > ValSize && LocSize == ValSize) {
271 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
272 MIRBuilder.buildTrunc(ValVReg, Copy);
273 return;
274 }
275
276 MIRBuilder.buildCopy(ValVReg, PhysReg);
277 break;
278 }
279 case CCValAssign::LocInfo::SExt:
280 case CCValAssign::LocInfo::ZExt:
281 case CCValAssign::LocInfo::AExt: {
282 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
283 MIRBuilder.buildTrunc(ValVReg, Copy);
284 break;
285 }
286 }
287 }
288
289 /// How the physical register gets marked varies between formal
290 /// parameters (it's a basic-block live-in), and a call instruction
291 /// (it's an implicit-def of the BL).
292 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
293
294 protected:
295 const DataLayout &DL;
296 };
297
298 struct FormalArgHandler : public IncomingValueHandler {
FormalArgHandler__anon7934bec90311::FormalArgHandler299 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
300 CCAssignFn *AssignFn)
301 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
302
markPhysRegUsed__anon7934bec90311::FormalArgHandler303 void markPhysRegUsed(unsigned PhysReg) override {
304 MIRBuilder.getMBB().addLiveIn(PhysReg);
305 }
306 };
307
308 struct CallReturnHandler : public IncomingValueHandler {
CallReturnHandler__anon7934bec90311::CallReturnHandler309 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
310 CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
311 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
312
markPhysRegUsed__anon7934bec90311::CallReturnHandler313 void markPhysRegUsed(unsigned PhysReg) override {
314 MIB.addDef(PhysReg, RegState::Implicit);
315 }
316
317 protected:
318 MachineInstrBuilder &MIB;
319 };
320
321 } // end anonymous namespace
322
lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<unsigned> VRegs) const323 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
324 const Function &F,
325 ArrayRef<unsigned> VRegs) const {
326 if (F.arg_empty())
327 return true;
328
329 // TODO: handle variadic function
330 if (F.isVarArg())
331 return false;
332
333 MachineFunction &MF = MIRBuilder.getMF();
334 MachineRegisterInfo &MRI = MF.getRegInfo();
335 auto DL = MF.getDataLayout();
336
337 SmallVector<ArgInfo, 8> SplitArgs;
338 unsigned Idx = 0;
339 for (auto &Arg : F.args()) {
340
341 // TODO: handle not simple cases.
342 if (Arg.hasAttribute(Attribute::ByVal) ||
343 Arg.hasAttribute(Attribute::InReg) ||
344 Arg.hasAttribute(Attribute::StructRet) ||
345 Arg.hasAttribute(Attribute::SwiftSelf) ||
346 Arg.hasAttribute(Attribute::SwiftError) ||
347 Arg.hasAttribute(Attribute::Nest))
348 return false;
349
350 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
351 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
352 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
353 [&](ArrayRef<unsigned> Regs) {
354 MIRBuilder.buildMerge(VRegs[Idx], Regs);
355 }))
356 return false;
357 Idx++;
358 }
359
360 MachineBasicBlock &MBB = MIRBuilder.getMBB();
361 if (!MBB.empty())
362 MIRBuilder.setInstr(*MBB.begin());
363
364 FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
365 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
366 return false;
367
368 // Move back to the end of the basic block.
369 MIRBuilder.setMBB(MBB);
370
371 return true;
372 }
373
lowerCall(MachineIRBuilder & MIRBuilder,CallingConv::ID CallConv,const MachineOperand & Callee,const ArgInfo & OrigRet,ArrayRef<ArgInfo> OrigArgs) const374 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
375 CallingConv::ID CallConv,
376 const MachineOperand &Callee,
377 const ArgInfo &OrigRet,
378 ArrayRef<ArgInfo> OrigArgs) const {
379 MachineFunction &MF = MIRBuilder.getMF();
380 const Function &F = MF.getFunction();
381 MachineRegisterInfo &MRI = MF.getRegInfo();
382 auto &DL = F.getParent()->getDataLayout();
383 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
384 const TargetInstrInfo &TII = *STI.getInstrInfo();
385 auto TRI = STI.getRegisterInfo();
386
387 // Handle only Linux C, X86_64_SysV calling conventions for now.
388 if (!STI.isTargetLinux() ||
389 !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
390 return false;
391
392 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
393 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
394
395 // Create a temporarily-floating call instruction so we can add the implicit
396 // uses of arg registers.
397 bool Is64Bit = STI.is64Bit();
398 unsigned CallOpc = Callee.isReg()
399 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
400 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
401
402 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
403 TRI->getCallPreservedMask(MF, CallConv));
404
405 SmallVector<ArgInfo, 8> SplitArgs;
406 for (const auto &OrigArg : OrigArgs) {
407
408 // TODO: handle not simple cases.
409 if (OrigArg.Flags.isByVal())
410 return false;
411
412 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
413 [&](ArrayRef<unsigned> Regs) {
414 MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
415 }))
416 return false;
417 }
418 // Do the actual argument marshalling.
419 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
420 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
421 return false;
422
423 bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
424 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
425 // From AMD64 ABI document:
426 // For calls that may call functions that use varargs or stdargs
427 // (prototype-less calls or calls to functions containing ellipsis (...) in
428 // the declaration) %al is used as hidden argument to specify the number
429 // of SSE registers used. The contents of %al do not need to match exactly
430 // the number of registers, but must be an ubound on the number of SSE
431 // registers used and is in the range 0 - 8 inclusive.
432
433 MIRBuilder.buildInstr(X86::MOV8ri)
434 .addDef(X86::AL)
435 .addImm(Handler.getNumXmmRegs());
436 MIB.addUse(X86::AL, RegState::Implicit);
437 }
438
439 // Now we can add the actual call instruction to the correct basic block.
440 MIRBuilder.insertInstr(MIB);
441
442 // If Callee is a reg, since it is used by a target specific
443 // instruction, it must have a register class matching the
444 // constraint of that instruction.
445 if (Callee.isReg())
446 MIB->getOperand(0).setReg(constrainOperandRegClass(
447 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
448 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
449
450 // Finally we can copy the returned value back into its virtual-register. In
451 // symmetry with the arguments, the physical register must be an
452 // implicit-define of the call instruction.
453
454 if (OrigRet.Reg) {
455 SplitArgs.clear();
456 SmallVector<unsigned, 8> NewRegs;
457
458 if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
459 [&](ArrayRef<unsigned> Regs) {
460 NewRegs.assign(Regs.begin(), Regs.end());
461 }))
462 return false;
463
464 CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
465 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
466 return false;
467
468 if (!NewRegs.empty())
469 MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
470 }
471
472 CallSeqStart.addImm(Handler.getStackSize())
473 .addImm(0 /* see getFrameTotalSize */)
474 .addImm(0 /* see getFrameAdjustment */);
475
476 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
477 MIRBuilder.buildInstr(AdjStackUp)
478 .addImm(Handler.getStackSize())
479 .addImm(0 /* NumBytesForCalleeToPop */);
480
481 return true;
482 }
483