| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 312 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
335 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
336 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
363 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
1141 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1316 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1455 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1791 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1792 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| H A D | ARMCallLowering.cpp | 556 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 47 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
121 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
|
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 57 unsigned constrainOperandRegClass(const MachineFunction &MF,
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2014 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
2046 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2068 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2069 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2093 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2094 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2095 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2119 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2142 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2186 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
|
| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1311 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1356 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1398 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
2069 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
2070 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2507 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2777 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
3264 CallReg = constrainOperandRegClass(II, CallReg, 0); in fastLowerCall()
5062 const unsigned AddrReg = constrainOperandRegClass( in selectAtomicCmpXchg()
5064 const unsigned DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg()
[all …]
|
| H A D | AArch64CallLowering.cpp | 407 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
|
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 477 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 446 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
|
| H A D | X86FastISel.cpp | 230 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
660 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3987 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
4009 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
4010 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
4011 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
4012 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2133 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2134 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
|