Lines Matching refs:constrainOperandRegClass

1108       constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));  in addLoadStoreOperands()
1110       constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));  in addLoadStoreOperands()
1311   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rr()
1312   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rr()
1356   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_ri()
1398   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rs()
1399   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rs()
1443   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rx()
1444   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rx()
2069   SrcReg = constrainOperandRegClass(II, SrcReg, 0);  in emitStoreRelease()
2070   AddrReg = constrainOperandRegClass(II, AddrReg, 1);  in emitStoreRelease()
2138   SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());  in emitStore()
2375   SrcReg = constrainOperandRegClass(II, SrcReg,  II.getNumDefs());  in emitCompareAndBranch()
2507     = constrainOperandRegClass(II, CondReg, II.getNumDefs());  in selectBranch()
2525   AddrReg = constrainOperandRegClass(II, AddrReg,  II.getNumDefs());  in selectIndirectBr()
2777     CondReg = constrainOperandRegClass(II, CondReg, 1);  in selectSelect()
3237       unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);  in fastLowerCall()
3264     CallReg = constrainOperandRegClass(II, CallReg, 0);  in fastLowerCall()
5062   const unsigned AddrReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
5064   const unsigned DesiredReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
5066   const unsigned NewReg = constrainOperandRegClass(  in selectAtomicCmpXchg()