Lines Matching refs:constrainOperandRegClass

312   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
335   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rr()
336   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rr()
363   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_ri()
527     ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);  in ARMMaterializeInt()
604       DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);  in ARMMaterializeGV()
680     ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);  in fastMaterializeAlloca()
1068       SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);  in ARMEmitStore()
1141   SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);  in ARMEmitStore()
1279       OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);  in SelectBranch()
1316   CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);  in SelectBranch()
1455   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1457     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);  in ARMEmitCmp()
1661   CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);  in SelectSelect()
1681     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);  in SelectSelect()
1682     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);  in SelectSelect()
1690     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);  in SelectSelect()
1791   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1792   SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);  in SelectBinaryIntOp()
2736     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);  in ARMEmitIntExt()
2992   DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);  in ARMLowerPICELF()